Synopsys integrates Zroute Multi-Threaded Router into IC Compiler

Synopsys has announced the integration of Zroute multi-threaded router into company’s IC Compiler. Zroute’s architecture incorporates advanced routing technology, such as native support of soft rules to enable lithography-friendly routing. By simultaneously considering the impact of manufacturing rules, as well as timing and other design goals, Zroute delivers high quality of results (QoR) and improved manufacturability.

About Synopsys’ IC Compiler
IC Compiler provides faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure. Older solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations. IC Compiler’s XPS technology breaks down the walls between these steps by extending physical synthesis to full place-and-route. IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of Synopsys’ best core technologies. It is a complete physical design system with everything necessary to implement next-generation designs, including physical synthesis, design planning, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization.

Antun Domic, Synopsys, said:

Zroute is an excellent example of Synopsys’ investment in R&D to help our customers stay ahead of the technology curve. Anticipating future requirements, we set out to develop a new router that not only could address the emerging issues of DFM (design-for-manufacturability), timing, and other design goals, but could do it much faster executing transparently on the new multi-core processors… Zroute has been very successful with early adopters, and we’re looking forward to bringing this exciting technology to all IC Compiler users…

Zroute is incorporated as a standard feature in IC Compiler, offering an alternate choice for routing technology which can be enabled by customers as required. Zroute was specifically developed as a concurrent optimization router to deal with future technical challenges. Rather than addressing these issues later in the flow, Zroute’s strategy reserves routing resources for yield optimizations at each step of the flow, enabling their impact to be considered simultaneously with other cost functions. Additionally, Zroute is multi-threaded at each of its internal steps. Its routing engines have demonstrated near-linear scalability of runtimes as the number of threads increases, promising significant speed-ups for IC Compiler customers transitioning to four- or eight-core platforms and beyond.

Zroute will be in limited production availability as a standard feature in IC Compiler in June 2008.

More info about Zroute router  can be found at Synopsys website.