Virtex-4 FPGA Deserializer Reference Design

Xilinx and Texas Instruments are going to release the Virtex-4 FPGA-based deserializer reference design, application note and evaluation module . Texas Instruments will release the evaluation module, consisting a circuit board and a set of preconfigured design files, to help prototyping and evaluating the performance of its high-speed ADCs featuring serialized LVDS outputs.

David Gamba, Xilinx, said:

By combining TI's leading ADC technology with the programmability and industry-leading high-speed serial performance of our Virtex-4 FPGAs, designers can leverage the evaluation module as a flexible and rapid prototyping environment for designing digital circuits that directly interface to the ADCs…

Developers can leverage the enormous serial-to-parallel processing capabilities and programmability of Xilinx Virtex-4 FPGAs to accelerate operations for specialized, high-performance functions. The ability to achieve much higher levels of overall system performance is especially important for multi-channel systems in applications such as broadcast, medical, instrumentation and wireless infrastructure.

About Xilinx Virtex-4 FPGAs
With more than 100 technical innovations, the Xilinx Virtex-4 family consists of 17 devices and three domain-optimized platforms; Virtex-4 LX FPGAs optimized for logic-intensive designs, Virtex-4 FX FPGAs optimized for high-speed serial connectivity and embedded processing, and Virtex-4 SX FPGAs optimized for high-performance signal processing.

High-Performance LVDS Interface
Built on the Virtex-4 LX25 platform, the Xilinx deserializer reference design accepts up to four simultaneous ADC channels and provides automatic de-skew and clock alignment functions. Each ADC output is serialized and transmitted through a separate LVDS serial pair. An independent frame clock and serial data clock are provided to allow for easy deserialization. The Xilinx reference design exploits the unique ISERDES dedicated logic in the I/O of the Virtex-4 devices to provide the necessary timing to accept these extremely fast input signals and translate into parallel output busses, which can be more easily integrated.

The serial LVDS interface provides several distinct benefits to the system designer. The lower pin count, both on the ADC and the FPGA, results in less routing lines, potentially fewer board layers, better immunity to external noise and extremely low crosstalk and injection of noise into the printed circuit board. These advantages translate directly into lower system costs and improved system reliability when compared to legacy ADC communication interface technology.

TI's ADS6000 Data Converters
The pin-compatible ADS6000 family consists of dual- and quad-channel, 12- and 14-bit ADCs at speeds of 80, 100, 125 MSPS (mega samples per second) to provide a simple upgrade path for customers designing communications, instrumentation and imaging products. The ADS6000 family features excellent signal-to-noise ratio of 73.2dB dBFS (70.3dBFS for the 12-bit family) with 83dBc of spurious free dynamic range at 50 MHZ input frequency while only consuming 420mW of power per channel at 125 MSPS (330mW/channel at 80 MSPS). The devices allow high system density for multi-channel applications. Visit www.ti.com/ads6425 for more details as well as pricing and availability information.

When combined with the ADS6000 family of ADC products, the TSW1200EVM allows for easy deserialization and offers a flexible evaluation environment for analysis. The EVM can be connected to a logic analyzer for data analysis or to TI's TSW1100, a high-speed CMOS data capture and analysis tool.

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The TSW1100EVM high-speed ADC LVDS evaluation module price is $649

Source: Xilinx

The reference design, including VHDL code, application note and test files are available (free of charge) on Xilinx website.