Verification Methodology Manual (VMM) Catalyst Program - Synopsys

Synopsys announced its Verification Methodology Manual (VMM) Catalyst Program to further accelerate widespread adoption of the industry-leading VMM for SystemVerilog. The VMM Catalyst Program is open to EDA vendors, silicon and verification IP companies.

George Zafiropoulos, Discovery Verification Platform at Synopsys, Inc, said:

The VMM is the industry-leading methodology for SystemVerilog. It is being used by hundreds of design teams around the world and is supported by Synopsys' full range of VMM-enabled tools, verification IP, services and training

The VMM Catalyst program helps meet the growing demand for productive and interoperable verification flows taking advantage of the full power of SystemVerilog. VMM-enabled EDA tools allow users to work at higher levels of abstraction, thereby increasing productivity. Verification IP created according to the VMM methodology allows for easy "plug-and-play" use in VMM testbenches.

VMM Methodology
The VMM verification methodology for SystemVerilog is the industry-leading, de facto standard for architecting robust, powerful and productive verification environments for complex electronic systems, systems-on-chips (SoCs) and IP. The VMM methodology is defined in the Verification Methodology Manual (VMM) for SystemVerilog, published by Springer. The manual, co-authored by verification experts from ARM and Synopsys, describes how to use SystemVerilog to create comprehensive verification environments using coverage-driven, constrained-random and assertion-based techniques, and specifies library building blocks for creating interoperable verification components.

Verification consultants with VMM expertise can quickly create or enhance their client's verification environment, without having to spend time learning or developing a non-standard methodology. Training companies can help verification teams rapidly adopt the best practices incorporated in the VMM methodology. Engineers will therefore be able to choose from an even wider array of VMM-enabled offerings to speed development and deployment of verification environments.

Scott Sandler, CEO of Novas, said:

The VMM methodology is a vital addition to the infrastructure needed to support the adoption of SystemVerilog. VMM provides both the building blocks necessary for rapid adoption of the language and the framework for a standard methodology…

At Novas, we've responded to growing customer demand to make our Verdi Automated Debug System VMM-enabled — qualifying our compilers against VMM-based descriptions, providing advanced visualization of class structures and dynamic data, and ensuring that our current and future SystemVerilog Testbench capability delivers maximum benefit for VMM users…

Corporate members of the VMM Catalyst Program can gain access to Synopsys VMM-enabled products such as VCS, Pioneer-NTB, the VCS Verification Library of bus protocol verification IP, and the SystemVerilog source code for the VMM Standard Library. This access enables the development and support of corporate members' respective VMM-enabled tools, IP, training and services. By providing these tools, verification IP and source code, Synopsys is accelerating the adoption of a complete and consistent methodology usage across all VMM Catalyst Program member companies. VMM Catalyst program members meeting certain requirements may also use Synopsys' "VMM-enabled" logo with their products or services to indicate interoperability with or support of the methodology.

Michael Hoyt, CEO of Paradigm Works, said:

Paradigm Works is at the forefront of deploying advanced methodologies for the functional verification of complex ICs…

The VMM methodology details proven verification practices engineers can leverage when using SystemVerilog, and the introduction of the VMM Catalyst program will further accelerate the rate of VMM adoption. Already today, half of Paradigm Works' clients, including leading systems and semiconductor customers worldwide, are using the VMM methodology…

Industry support from more than 50 firms and widespread customer adoption has established the VMM methodology as the de facto standard methodology for verifying complex electronic chips.

Further reading: Synopsys Verification Methodology Manual (VMM) Catalyst Program