Verification Kit for Wireless and Consumer SoC - Cadence

Cadence announced its new verification kit for wireless and consumer SoC design. This verification kit helps  engineers to adopt advanced verification techniques. The new kit addresses key challenges engineers face when designing and verifying SoC designs: ensuring comprehensive verification of the design, enabling re-use, managing low-power modes typical in today's SoCs, ensuring hardware-dependent software coverage, and accomplishing the verification within very stringent time-to-market timelines.

The new SoC Functional Verification Kit will be featured at the CDNLive! Silicon Valley technical conference, scheduled for Sept. 10 to 12, in San Jose, Calif.

Moshe Gavrielov, Cadence Verification Division, said:

With today's wireless and consumer chip designs becoming increasingly complex, design teams are under growing pressure to apply more effective verification methods and technology…

…The SoC Functional Verification Kit delivers a solution spanning the full verification process to ease adoption of advanced verification capabilities for design and verification teams.

The Cadence SoC Functional Verification Kit provides a proven end-to-end methodology that extends from block-level verification to chip- and system- level advanced verification and includes automated methodologies for implementation and management. The kit provides complete example verification plans, transaction-level and cycle-accurate models, design and verification IP, scripts and libraries - all proven on a wireless segment representative design and delivered through applicability consulting.

The applicability consulting included with the kit provides complete and interactive guidance for performing predictable and repeatable verification of blocks, clusters, full chips, and SoCs, and enables design teams to quickly and easily adopt the Cadence Incisive Plan-to-Closure Methodology.

Graham Budd, Processor Division at ARM:

Functional verification of SoC designs is one of the most difficult and time-consuming challenges our semiconductor and systems partners face today…

…Through the kits initiative and ARM collaboration, the Cadence SoC Functional Verification Kit directly addresses these challenges and helps our mutual customers get their products to market more efficiently.

The SoC Functional Verification Kit includes design and verification IP from Cadence and third parties, including an accurate high-speed model of the ARM968E-S processor, AMBA PrimeCell IP including interconnect and peripherals, and the ARM RealView Development Suite debugger, USB 2.0 from ChipIdea, and 802.11 from WiPro. The kit includes three main flows: architectural, RTL block to chip, and system-level.

The Cadence Incisive Plan-to-Closure Methodology will support the Open Verification Methodology or OVM in Q4 this year. The OVM is based on Cadence's Incisive Plan-to-Closure URM module and Mentor's Advanced Verification Methodology module.

More info: Cadence Wireless and Consumer SoC Verification Kit