TSMC Introduces Reference Flow 8.0 for 45nm Process Design

Taiwan Semiconductor Manufacturing Company, Ltd., (TSMC) introduced Reference Flow 8.0, the latest generation of TSMC’s  design methodology product. Reference Flow 8.0 supports TSMC's 45nm process technology with advanced standard cell, standard I/O, and SRAM compiler. Key features includes statistical timing analysis for intra-die variation, new dynamic low-power design methodologies and automated DFM hot-spot fixing.

Reference Flow 8.0 supports TSMC's Active Accuracy Assurance initiative, which defines standards of accuracy for all partners in TSMC's design ecosystem. Reference Flow 8.0 focuses on ease of use, providing a reference of qualified design building blocks that give designers a proven path from specification to tape out. The new product not only supports 45nm, 65nm, and 90nm process technologies, but also provides mature design flows for mainstream technologies from 0.13-micron to 0.25-micron.

Enhanced Statistical Timing Analysis
Reference Flow 7.0 introduced the first foundry design methodology to include inter-die statistical timing analysis to accurately determine the timing effects of manufacturing process variations. Reference Flow 8.0 expands on this capability by offering intra-die statistical timing analysis along with statistical leakage and statistical timing optimization. Statistical leakage provides a more precise analysis of leakage that reflects actual manufacturing outcomes. Statistical timing optimization helps reducing the need for over-design and enables more effective timing closure. These features enable designers to optimize design margins and increase yields.

Design for Manufacturability (DFM)
Reference Flow 8.0 provides further improvements in DFM methodology, which allows designers to address potential manufacturing challenges during the design process, rather than post-processing after tape-out. Among the new features are automated DFM hot spot fixing to eliminate the need for manual correction and DFM electrical variability consideration, which monitors parametric performance shifts caused by DFM effects. Increased automation, integrated analysis, and optimization capabilities shorten design cycles by enabling designers to anticipate DFM issues and quickly take necessary measures.

Low Power Design
Reference Flow 8.0 includes a number of new and innovative power reduction techniques including TSMC's new AVS (Adaptive Voltage Scaling) which enables reduction of active power consumption for next-generation mobile devices. A dual power rail SRAM design enables more dynamic power reduction, long channel device innovations cut power consumption due to leakage. Coarse-grain power gating and other techniques employed in standard cells further reduce overall standby leakage. The Common Power Format (CPF) enables significant improvement in automated low-power design methodology. Together these features extend battery life for portable devices and reduce packaging and cooling costs.

Further reading: TSMC Reference Flow 8.0 for 45nm Design