Toshiba Orion V1.0 Design Kit based on Synopsys IC Compiler Place and Route Solution

Toshiba has completed the release of  Orion V1.0 design kit based on the Synopsys implementation toolset including the IC Compiler place-and-route solution. With this release, IC Compiler is now available to all designers at Toshiba, giving Toshiba designers a highly automated multi-voltage flow with tight correlation to other Synopsys technologies such as the PrimeTime SI sign-off solution and Star-RCXT extraction solution.

About IC Compiler
IC Compiler is Synopsys' next-generation place-and-route system. It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure. Current-generation solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations. IC Compiler's Extended Physical Synthesis (XPS) technology breaks down the walls between these steps by extending physical synthesis to full place-and-route. IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of the best Synopsys core technologies. It is a comprehensive place-and-route system with features necessary to implement next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization.

Toshiba's designs often contain multiple operating modes, which benefit from IC Compiler's truly concurrent MCMM optimization that provides increased accuracy and faster time-to-results compared to other solutions relying on sequential approaches. All designs benefit from comprehensive leakage power management in IC Compiler as well as high-performance optimizations driven by IC Compiler's XPS (extended physical synthesis) technology.

The latest chip completed by Toshiba using IC Compiler is a 2-million-instance design comprised of multiple subsystems running at over 300 megahertz (MHz) with nested voltage levels. Achieving the combination of schedule, performance, low power and integrated functionality was an important achievement for Toshiba with this design targeting the hyper-competitive mobile phone market. IC Compiler's integration with the Galaxy Design Platform was a notable enabler in the development of this chip. This tight integration provides designers access to the latest technologies such as test compression using DFT MAX, strong link synthesis using Design Compiler topographical technology, and tight correlation to the PrimeTime static timing analysis (STA) suite.

Source: Synopsys - IC Compiler place-and-route solution