TD-SCDMA Digital Front-End (DFE) Reference Design - Xilinx

Xilinx , Inc., in partnership Multiple Access Communications (MAC) Ltd, announced the immediate availability of a TD-SCDMA Digital Front End (DFE) reference design solution based on the Xilinx System Generator for DSP tool. TD-SCDMA Digital Front-End Reference Design solution reduces the development time required for TD-SCDMA DFE radio application development.

About Xilinx TD-SCDMA DFE Reference Design Solution
The TD-SCDMA DFE reference design solution is enabled by Xilinx high-performance Virtex -4 platform FPGAs. The platform offer high performance and cost-effective DSP processing capability, and its  in-field upgrades feature make the base station more adaptable to evolving standards and technologies.

Dr Wilson Oon, Xilinx Asia-Pacific, said:

Xilinx and MAC Ltd have produced a reference design solution that offers a significant time-to-market advantage for OEMs developing TD-SCDMA radio subsystems…

As operators strive to reduce capital and operating costs, wireless OEMs are looking to exploit the lower power and additional flexibility that FPGAs bring to digital radio applications. They are also looking for an architecture that can scale as TD-SCDMA evolves to meet the increasing demand for higher performance and system throughput…

The solution enables users to construct 3GPP-compliant DFE designs for a wide variety of base station configurations. It includes example reference designs, full-speed working demo and complete IP (Intelectual property) library, including optimized System Generator IP Blocks for digital up conversion (DUC) and digital down conversion (DDC) functions.

David Kenyon, MAC, said:

The market is looking for flexible, cost-effective solutions which can be developed from concept-to-production as quickly and easily as possible…

The combination of the Xilinx Virtex platform FPGA and Mac Ltd's proven expertise in developing wireless signal processing solutions has allowed us to develop a TD-SCDMA DFE reference design that uses FPGA resources very efficiently and fits into very cost-effective devices…

Using TD-SCDMA DFE reference design solution, developers can save many man-months of algorithm development and many man-years of hardware development time. Solution provides  from concept-to-production path for digital radio application development. The IP library encapsulates the signal processing functions that determine compliance with the 3GPP requirements in such a way that complexity of these functions is hidden from the library user.

The TD-SCDMA DFE reference design supports up to 6 carriers per antenna and offers a flexible intermediate frequency input or output. DUC performance highlights are an EVM of 1.6% RMS and Adjacent Channel Leakage Ratio (ACLR) >80dB, for an occupied bandwidth of >99.9%. The DDC block provides Adjacent Channel Selectivity (ACS) >75dB, blocking >80dB and a low latency Signal Path Delay of just 14.9us.

About TD-SCDMA

TD-SCDMA (Time Division-Synchronous Code Division Multiple Access) is a 3G mobile telecommunications standard, being pursued by the Chinese Academy of Telecommunications Technology (CATT), Datang and Siemens AG, in an attempt not to be dependent on Western technology. This is likely primarily for practical reasons, other 3G formats require the payment of patent fees to a large number of western patent holders. TD-SCDMA is based on spread spectrum technology which makes it unlikely that it will be able to escape completely the payment of license fees to western patent holders. The launch of an operational system was initially projected by 2005 but is now projected by 2007.

The S in TD-SCDMA stands for synchronous, which means that uplink signals are synchronized at the base station receiver, achieved by continuous timing adjustments. This reduces the interference between users of the same timeslot using different codes by improving the orthogonality between the codes, therefore increasing system capacity, at the cost of some hardware complexity in achieving uplink synchronization.

TD-SCDMA uses TDD, in contrast to the FDD scheme used by W-CDMA. By dynamically adjusting the number of timeslots used for downlink and uplink, the system can more easily accommodate asymmetric traffic with different data rate requirements on downlink and uplink than FDD schemes. Since it does not require paired spectrum for downlink and uplink, spectrum allocation flexibility is also increased. Also, using the same carrier frequency for uplink and downlink means that the channel condition is the same on both directions, and the base station can deduce the downlink channel information from uplink channel estimates, which is helpful to the application of beamforming techniques.

TD-SCDMA also uses TDMA in addition to the CDMA used in WCDMA. This reduces the number of users in each timeslot, which reduces the implementation complexity of multiuser detection and beamforming schemes, but the non-continuous transmission also reduces coverage (because of the higher peak power needed), mobility (because of lower power control frequency) and complicates radio resource management algorithms.

The free Xilinx TD-SCDMA DFE reference design is available now for qualified customers. The Xilinx ML402 development board and XtremeDSP Development Kit for Virtex-4 FPGAs can be purchased separately.

Resources:

• Free Xilinx TD-SCDMA DFE Reference Design
• wikipedia.org TD-SCDMA