Synopsys Supports TSMC Reference Flow 8.0 for 45nm Design

Synopsys support for TSMC's Reference Flow 8.0 and 45nm process technologies. Synopsys is supporting Reference Flow 8.0 in its Galaxy Design Platform, Discovery Verification Platform, and design for manufacturing (DFM) products. TSMC Reference Flow 8.0 includes statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies. Advanced power management techniques include multi-voltage and MTCMOS power gating, as well as more commonly used techniques such as clock gating and multi-threshold, available through the Synopsys Galaxy Design Platform.

About TSMC Reference Flow 8.0 Support
Reference Flow 8.0 incorporates comprehensive Synopsys-based RTL-to-GDSII solution using the Galaxy Design Platform for RTL synthesis, physical implementation and sign-off, and the Discovery Verification Platform with VCS, HSPICE, and HSIM/Nanosim for RTL verification and circuit simulation.

The Synopsys Discovery Verification Platform enables power-aware simulation, formal equivalence checking, and static analysis of designs that use advanced power management techniques such as multiple power domains, level shifters, isolation cells, and retention memory elements. Advanced multi-voltage designs have been taped out with TSMC's manufacturing technology using Synopsys power management solutions.

Reference Flow 8.0 takes advantage of new capabilities available through the Galaxy Design Platform and PrimeYield design-yield analysis tool suite for 45nm readiness. For productivity gains during implementation, designers can use concurrent yield optimization for critical area reduction and automated hot-spot fixing within IC Compiler. For analysis, designers can now use PrimeYield LCC to perform parametric (timing) analysis in addition to functional hot-spot analysis. To enable this, the PrimeYield and Star-RCXT tools support advanced features such as Virtual CMP (VCMP) analysis engine.

Synopsys has worked with TSMC on a comprehensive variation-aware flow that allows designers to reduce margins, improve design robustness, and enhance parametric yield. The Synopsys variation-aware analysis solution consists of three important components: The Composite Current Source (CCS)-based statistical library, sensitivity-based extraction using the Star-RCXT VX tool and statistical timing analysis technology in the PrimeTime VX tool. With uncertainties introduced by the wide variation in device and interconnect at the sub-45nm level, customers can apply this solution to their complex 45nm system-on-chip (SoC) designs today. Additional Synopsys enhancements featured in TSMC Reference Flow 8.0 include advanced design-for-test (DFT) capabilities and support of TSMC 45nm design rules.

As an integral part of the reference flow, Galaxy support includes:

• Design Compiler and Design Compiler topographical technology logic synthesis
• Power Compiler multi-voltage power management
• DFT MAX 1-pass test synthesis
• Leda RTL Checker
• JupiterXT physical planning
• PrimeTime, PrimeTime SI, and PrimeTime VX static timing and signal integrity sign-off
• PrimeRail power network sign-off
• PrimeTime PX full-chip power analysis
• IC Compiler physical implementation
• Star-RCXT extraction
• Hercules PVS physical verification
• PrimeYield LCC for design-for-yield analysisSynopsys Professional Services provides expertise in chip implementation and flow deployment with Reference Flow 8.0. Synopsys also distributes TSMC libraries through the DesignWare Library.
• TetraMAX automatic test pattern generation (ATPG)

Further reading: Synopsys Supports TSMC Reference Flow 8.0 for 45nm Design