Synopsys PCI Express compliance and USB 2.0 IP certification

Synopsys announced the compliance of its PCI Express and certification of its USB 2.0 IP solutions for the Common Platform technology available from Samsung, IBM and Chartered. Synopsys’ DesignWare PHY for PCI Express and digital controllers are the first 65-nm IP to pass the PCI Express 1.1 compliance testing by the PCI-SIG. Synopsys’ DesignWare USB 2.0 nanoPHY IP in the Common Platform 90-nm process is the first implementation to have earned Hi-Speed USB ‘On-the-Go’ (OTG) logo-certification by the USB IF.

The Synopsys DesignWare Mixed-Signal IP, including a PCI Express silicon demonstration, will be presented in the IBM/Common Platform booth #2460 at the upcoming Design Automation Conference on June 4 -7 in San Diego.

Having the latest DesignWare PHY for PCI Express pass the PCI-SIG compliance test helps ensures interoperability and standards compliance. It also demonstrates correct operation, significantly reducing design risks associated with these complex interfaces. Synopsys is currently the only company to deliver a comprehensive portfolio of integrated PCI Express IP solutions comprised of the PIPE compliant PHY and PCI Express digital controllers for Endpoint, Root Complex, Dual Mode, Switch and Bridge applications, as well as verification IP. Synopsys' PHY IP for PCI Express has the lowest power (30 to 50 percent lower than competitive solutions) as well as high performance margins and small die area. Furthermore, the PHY IP provides advanced built-in diagnostics and production ATE vectors.

Similarly, the Synopsys DesignWare USB 2.0 nanoPHY IP - which is also implemented in the Common Platform 90-nm process and manufactured at both IBM and Chartered — was certified by the USB Implementers Forum to conform to the requirements of the Hi-Speed USB 2.0 and Hi-Speed USB OTG specifications. The 65-nm single-GDSII version of the USB 2.0 nanoPHY has been taped out by all three partners and the first certification is under way. The DesignWare USB IP solution includes the low-power, low-area USB 2.0 nanoPHY with the Hi-Speed OTG digital controller - which operates as either a USB 2.0-compliant peripheral or an OTG host - and verification IP. Using the Common Platform design guidelines, the DesignWare USB 2.0 nanoPHY has been specifically designed to improve chip yield while reducing sensitivity to process variation and chip and board parasitics. Using a single GDSII file, IBM and Chartered fabricated identical test chips. Synopsys proved identical operation of the complex analog devices by performing a detailed analysis across a range of operating conditions.

The DesignWare IP for PCI Express and USB solutions complement the 65-nm and 90-nm reference flow delivered by Synopsys for the Common Platform technologies. The Synopsys solution combines certified IP components and a proven reference flow, allowing designers to complete their designs more quickly while increasing yield and reducing risk.

The DesignWare PHY IP, digital controllers, and verification IP for PCI Express are available today in the IBM 10LP/10SF and the Chartered 65LP/65G foundry processes in 1-lane, 2-lane, 4-lane, and 8-lane configurations.

Further reading:  Synopsys PCI Express and USB 2.0 IP Solutions