Sun Releases OpenSPARC T2 RTL Processor Design to Open Source Community

Sun Microsystems announced the release of company’s OpenSPARC T2 RTL (Register Transfer Level) processor design to open source community (GPL license).  The OpenSPARC T2 is derived from the UltraSPARC T2 processor, which offers eight cores and eight threads per core, and integrating all the key functions of a server on a single chip: computing, networking, security, I/O, and also a tight integration with the Solaris operating system.

David Yen,  Sun Microelectronics, said:

Open sourcing the UltraSPARC T1 processor design was such a new concept it created some angst and a fair amount of debate before we pulled the trigger.. But there was no debate associated with T2; we’ve seen the success of open sourcing hardware, and the interest it has created in the developer, university and customer communities. The number of downloads have been impressive and confident we’re expanding the market for Sun technology.

About The OpenSPARC T2 Processor
The commodity UltraSPARC T2 processor delivers a 64-way system on a single chip. It’s the industry’s first processor to bring together the key functions of multiple systems-virtualization, processing, networking, security, floating point units and accelerated memory access. With the UltraSPARC T2 processor Sun extended its lead in eco performance by combining the industry’s lowest power consumption with double the cores, 16 times the threads, 4 times the throughput, with on-chip network and security functionality.

In December 2005, Sun announced it would publish the specifics for the UltraSPARC T1 processor, making it the first major processor design to be offered to the open source community. And since the launch of the OpenSPARC T1 processor in March 2006, over 6,500 copies of the OpenSPARC T1 processor RTL have been downloaded worldwide. Through the OpenSPARC technology program, Sun helps community members to build on proven technology at a dramatically low cost, and helps to drive down the cost of implementing designs into different technologies and products. The OpenSPARC T1 and OpenSPARC T2 processor RTL files can be downloaded at  http://www.opensparc.net.

OpenSPARC community has also been selected as part of Sun’s Open Source Community Innovation Awards Program. Announced last week, the multi-year program is designed to foster innovation and recognize some of the most interesting open source initiatives within Sun. Sun has selected six communities for the program’s first year: GlassFish, NetBeans, OpenJDK, OpenOffice.org, OpenSolaris and OpenSPARC. Prizes are expected to total at least $1 million (USD) a year.

Beginning mid-January 2008, the six open source communities will announce the details around the individual programs. Each community will have its own rules and judging criteria. Prize winners will be announced in August 2008. To follow contest updates and major developments, visit: http://www.sun.com/opensource/awards

OpenSPARC T2 Overview

Source: OpenSPARC T2 Core Microarchitecture Specification
(http://opensparc-t2.sunsource.net/specs/OpenSPARCT2_Core_Micro_Arch.pdf)

OpenSPARC T2 is a single chip multi-threaded (CMT) processor. OpenSPARC T2 contains eight SPARC physical processor cores. Each SPARC physical processor core has full hardware support for eight strands, two integer execution pipelines, one floating-point execution pipeline, and one memory pipeline. The floating-point and memory pipelines are shared by all eight strands. The eight strands are hardpartitioned into two groups of four, and the four strands within a group share a single integer pipeline. While all eight strands run simultaneously, at any given time at most two strands will be active in the physical core, and those two strands will be issuing either a pair of integer pipeline operations, an integer operation and a floating-point operation, an integer operation and a memory operation, or a floatingpoint operation and a memory operation. Strands are switched on a cycle-by-cycle basis between the available strands within the hard-partitioned group of four using a least recently issued priority scheme. When a strand encounters a long-latency event, such as a cache miss, it is marked unavailable and instructions will not be issued from that strand until the long-latency event is resolved. Execution of the remaining available strands will continue while the long-latency event of the first strand is resolved.

Each SPARC physical core has a 16 KB, 8-way associative instruction cache (32-byte lines), 8 Kbytes, 4-way associative data cache (16-byte lines), 64-entry fullyassociative instruction TLB, and 128-entry fully associative data TLB that are shared by the eight strands. The eight SPARC physical cores are connected through a crossbar to an on-chip unified 4 Mbyte, 16-way associative L2 cache (64-byte lines). The L2 cache is banked eight ways to provide sufficient bandwidth for the eight SPARC physical cores. The L2 cache connects to four on-chip DRAM controllers, which directly interface to a pair of fully buffered DIMM (FBD) channels. In addition, an on-chip PCI-EX controller, two 1-Gbit/10-Gbit Ethernet MACs, and several on-chip I/O-mapped control registers are accessible to the SPARC physical cores. Traffic from the PCI-EX port coherently interacts with the L2 cache.

OpenSPARC T2 Chip Block Diagram

OpenSPARC T2 Components:

• SPARC Physical Core
  Each SPARC physical core has hardware support for eight strands. This support consists of a full register file (with eight register windows) per strand, with most of the ASI, ASR, and privileged registers replicated per strand. The eight strands share the instruction and data caches and TLBs. An auto-demap feature is included with the TLBs to allow the multiple strands to update the TLB without locking. There is a single floating-point unit within each SPARC physical core for a total of 8 on a T2 chip. Each floating-point unit is shared by all eight strands and fully pipelined. The theoretical floating-point bandwidth is 11 Giga Floating Point Ops (GFlops) per second making the T2 an excellent floating-point processor.
• SPARC System-On Chip (SoC)
  Each SPARC physical core is supported by system on chip hardware components.

OpenSPARC T2 currently does not include PCI-Express and 10Gigabit Ethernet design implementation due to current legal restrictions. Equivalent models may be available in the subsequent releases of OpenSPARC T2.

More info: Sun OpenSPARC