SPEAr Basic Customizable ARM-based SoC - STMicroelectronics

STMicroelectronics (ST) has announced the SPEAr BASIC,  a new member of SPEAr (Structured Processor Enhanced Architecture) family. SPEAr BASIC is a digital engine consisting of two main parts: an ARM based architecture and an embedded programmable logic block. The new customizable ARM-based SoC integrates an advanced ARM926EJ-S processor core with two16k memory caches, running at 333MHz, for data and instructions and up to 300K gates (ASIC-equivalent) of embedded configurable logic. SPEAr Basic is targeted for wide variety of embedded applications, including digital photo frames, printers, fax machines and VoIP devices.

ST’s SPEAr Basic Customizable ARM-based SoC - Block Diagram

Loris Valenti,  ST, stated:

Leveraging ST’s market-leading configurable SoC architecture, the SPEAr Basic provides a seamless cost-reduction path for applications where price/performance is key… The new SPEAr device speeds the adoption of customized 65nm IC solutions with an ASIC-like flexibility, at a fraction of the development time and cost required by a full-custom design approach. In addition, customers can easily re-use software developed for previous SPEAr family members. All this makes the SPEAr Basic the best time-to-market solution for a variety of slots, with no compromise in features and performance…

SPEAr Basic Customizable ARM-based SoC provides memory interfaces supporting LP-DDR and DDR2 memories and a large connectivity-IP (intellectual property) portfolio, including Fast-IrDA interface, Ethernet MAC, three USB2.0 ports with embedded PHYs, UART, SPI, I2C, up to 102 fully programmable GPIOs and a total of 72 Kbytes of SRAM and 32 Kbytes of Boot ROM.

For printer applications, SPEAr Basic Customizable ARM-based SoC provides a full set of image-pipeline accelerators, from color-space conversion to raster-file generation, a hardware JPEG codec, a rotation engine, an LCD controller (up to 1024×768, 24-bits per pixel) and a SDIO/MM card interface.

Additional features include a 10-bit analog-to-digital converter, a crypto accelerator based on ST’s proprietary C3 IP, a Flexible Static Memory controller (NOR/NAND Flash and SRAM), TDM (Time-Division Multiplexing) and SLIC (Serial Link and Interrupt) controllers and a camera interface, providing unprecedented scale of integration and flexibility.

Key features of SPEAr Basic Customizable ARM-based SoC:

• ARM926EJ-S core at 333 MHz
• 300-Kgate customizable logic array with 102 dedicated general-purpose I/Os and 64 Kbytes + 8 Kbytes of configurable internal memory
• 32-Kbyte boot ROM
• Multilayer AMBA 2.0 compliant bus with fMAX @ 166 MHz
• Ethernet 10/100 MAC with MII interface to external PHY
• USB 2.0 device with integrated PHY
• 2x USB 2.0 host with integrated PHY
• High-performance 8-channel DMA
• External DRAM memory interface:
  • 8/16 bits (LP-DDR @ 166 MHz)
  • 8/16 bits (DDR2 @ 333 MHz)
  • 2 banks available
• I2C master/slave mode – high, fast and slow speed
• SPI master/slave up to 50 Mbit/s
• Flash interface: SPI serial (up to 50 Mbit/s)
• UART up to 460.8 Kbit/s
• IrDA (FIR/MIR/SIR) from 9.6 Kbit/s to 4 Mbit/s
• 10-bit ADC, 1 MSPS, 8 inputs
  • HW supporting up to 13.5 bits at 8 KSPS by oversampling and accumulation
• JPEG codec accelerator
• System controller
• 3 pairs of 16-bit independent timers with programmable prescaler
• Real-time clock
• Watchdog
• Additional internal control registers
• JTAG (IEEE 1149.1) interface
• Low power consumptiotechnology
• C3 crypto accelerator
  • DES/3DES/AES/SHA1
• Dynamic power-saving features
• LFBGA 289 package (15 x 15 x 0.8 mm)

SPEAr Basic’s software-configurable power-saving modes address most recent ecological and power-sensitive specifications. The device supports most popular embedded operating systems including Linux, VxWorks, ThreadX and Windows CE.

The SPEAr Basic comes complete with an evaluation board that allows quick and easy setup, design and testing of the devices. Using the SPEAr Plus600 Development kit and its external FPGA, which mirrors the SoC’s internal configurable logic block, designers can proceed with software and hardware development without waiting for final validation. Once the customer’s SoC passes the functional qualification, full production can typically ramp up in eight to ten weeks’ time from the final RTL availability.

Samples of SPEAr Basic Customizable ARM-based SoC are available now. Volume production is planed to start in Q3 2008. Price of  SPEAr Basic is $6 (20K unit qty).

Customizable ARM-based SoC

More information about SPEAr Basic Customizable ARM-based SoC can be found at STMicroelectronics website.