Single Chip Baseband Processor for W-CDMA Base Station - TMS320TCI6488

Texas Instruments announced TMS320TCI6488, three-core DSP (digital signal processor) for Wideband Code Division Multiple Access (W-CDMA) base stations. The chips running at 3GHz (1GHz per core) of speed and supports all  requirement to build a macro base station on a single chip.

The TMS320TCI6488 is based on TI's TMS320C64x+ platform. The processing power of the C64x+ DSP provides dynamic support of both voice and data transmission with low latency, ensuring a quality experience for consumers and service providers alike.

The TMS320TCI6488  features Viterbi (VCP2) and Turbo (TCP2) Coprocessors. It also has the built-in capability designed to support W-CDMA intensive calculations. The chip can handle search and rake receiver, the most computationally intensive tasks in W-CDMA.

The TMS320TCI6488  includes OBSAI and CPRI W-CDMA standardized antenna interfaces on chip. These antenna interfaces support up to 48 antenna streams per base station, allowing multi-antenna and multi-sector base stations.

The TMS320TCI6488  also includes Gigabit Ethernet port for network interface. The TCI6488’s Serial RapidIO allows base station designers to easily move data across the system fabric

The TMS320TCI6488 includes optimized software libraries for W-CDMA, enabling channel-power optimizing.

Jerold Givens, TI, said:

…evolving system requirements and feature additions make deploying adaptable network equipment a requirement for wireless networks. Operating on TI's powerful DSP core, the performance, capability and efficiency of the TCI6488 make it the only comprehensive baseband solution for W-CDMA base stations on the market…

TI's broad portfolio of analog products includes clocking solutions for the TMS320TCI6488 . The OBSAI and CPRI compliant CDCL6010 jitter cleaning phase-locked loop (PLL) and CDLC1810 buffer are both designed to be fully compatible with the TCI6488. The CDCL6010 jitter cleaner and buffer has an integrated on-chip voltage-controlled oscillator (VCO) and PLL which reduce frequency jitter and maintain the signal integrity of the DSP. The CDCL1810 is a pin compatible clock buffer, interchangeable with the CDCL6010 for clock distribution that does not require jitter cleaning.

The TMS320TCI6488 complements recently announced processors such as the TMS320TCI6487 and TMS320TCI6482, along with a variety of other high performance analog products from TI, and a suite of solutions that add to the most robust portfolio of multi-standard wireless and communications infrastructure technology in the industry.

The TMS320TCI6488  is currently in sampling

Source: TI