Sierra’s Place and Route Innovation for 45nm Design

Sierra Design Automation introduced several innovations of its place and route (P&R) platform, addressing 45nm design challenges including complex design rule checks (DRCs) and interconnect resistance variation. The new capabilities are targeted to broad range of market segments, including handheld, wireless, graphics, set-top boxes, networking and processors.

The scaling of process technology into 45nm regime is characterized by a significant increase in interconnect resistance. The resistance of interconnect is one of the integral 45nm implementation challenges due to its impact on circuit performance and reliability of clock trees. Engines such as placement, CTS and routing need to optimize for increased resistance and large variation of resistance across different process corners by optimally trading-off circuit performance, power consumption, and die size. Traditionally, techniques such as buffering were used to address RC problems in earlier nodes. But at 45nm, such techniques break down, resulting in over-buffering causing increased power consumption and die-size. A dynamic tradeoff between buffering the wire versus assigning it to less resistive layers is essential in order to achieve the best delay/area trade-off.

About Sierra Design Automation
Sierra Design Automation’s world-class electronic design automation (EDA) team is focused on providing semiconductor designers with innovative integrated circuit (IC) and system-on-chip (SoC) implementation solutions that comprehensively address the performance, capacity, time-to-market, and variability challenges occurring at the 65nm, 45nm, and smaller process nodes.

Sierra Olympus-SoC
Olympus-SoC, Sierra’s flagship product, provides the next generation place and route system that concurrently addresses variations in lithography, process corners and design modes. It is built on Sierra’s design for variability technology, Sierra Pinnacle, the customer-proven and industry leading physical implementation solution. Technology highlights include lithography-driven detailed router, embedded signoff quality timing engine, adaptive variability engine in addition to an open architecture and ultra-compact database that can handle extremely large capacities.

45nm also brings with it increased complexity in routing design rules and design for manufacturability (DFM) requirements for an increased yield. Conventional routing approaches which rely on extensive post-processing to address complex design rules and DFM metrics will no longer work at 45nm. These rules have to be modeled much earlier in the routing flow in order to achieve DRC cleanliness and higher DFM scores.

Sierra delivers the following key technologies to address the 45nm requirements:

• The FalconGR global routing technology assigns layers dynamically throughout the P&R flow and is embedded within every engine such as placement, CTS and detailed routing. The FalconGR routing technology ensures that resistive critical wires are assigned to layers with the least resistance and achieves an optimal delay/area tradeoff. This prevents over-buffering of the circuit and achieves the best performance.
• The global, track and detailed routing engines have been enhanced to model complex 45nm design rules and recommended DFM rules throughout the routing flow, which eliminates the need for expensive post-processing to achieve DRC and DFM closure. Advanced techniques such as via optimization, "liquid" wire spreading and a customizable DRC rule interface enables designers to achieve higher DFM scores.
• The Multi-Corner CTS technology automatically minimizes intra- and inter-corner skew and insertion delays in a single run. Large resistance variations across process corners are seamlessly handled resulting in a clock tree implementation that works across all the process corners. This requires a dynamic measurement of cell and wire delays in the clock tree across different process corners concurrently during clock tree construction.

These technologies, in conjunction with Sierra's unique variation and litho-driven design closure implementation system deliver the most comprehensive P&R solution for 45nm and below. Since its announcement last year, Sierra's Olympus-SoC P&R platform has been actively adopted by high-end customers looking for a next-generation physical design solution to implement 65nm and 45nm designs.

Source: Sierra Design Automation - Place and Route Innovation for 45nm Design