Renesas Adopt Cadence Encounter RTL Compiler

Cadence Design Systems, Inc. announced that Renesas Technology Corp. has adopted Cadence Encounter  RTL Compiler in its ASIC design kits. Renesas is extending their current ASIC kits and methodologies to add support for Encounter RTL Compiler.

Renesas successfully evaluated Encounter RTL Compiler on large high-performance ASIC blocks. The resulting blocks achieved greater timing improvement, reduction in area, dynamic power reduction and simpler clock-tree.

Encounter RTL Compiler with global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route. This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness.

Source Cadence