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Quartus II Design Software v.7 from Altera
Posted in Development Tools, PLD, FPGA, ASIC,..., AlteraOn Wednesday, March 21, 2007
Altera introduced new version of it’s Quartus II software (Subscription and free Edition). The new version support the entire 65-nm Cyclone III FPGA family. Quartus II technology allow designers to explore the full potential of the Cyclone III.
Jordan Plofsky, Altera, said:
Our easy-to-use Quartus II software, together with low-cost Cyclone III FPGAs, addresses designs ranging from 5K to 120K logic elements (LEs), expanding programmable logic into a wider array of cost-sensitive applications…
Quartus II v 7.0 supports the new Cyclone III family, including the EP3C120 device with 4 Mbits of memory, 120K LEs and 288 multipliers. These features include TimeQuest timing analyzer for easy and quick timing closure, incremental compilation for fast compile times and team-based design, PowerPlay power analysis and optimization tools for minimal power consumption, and SOPC Builder and DSP Builder tools for system-level design.
The free Quartus II Web Edition software features:
- Integrated VHDL, Verilog HDL, and SystemVerilog synthesis
- Place-and-route, verification, and programming functions
- SOPC Builder system generation software
- Resource optimization advisor
- TimeQuest timing analyzer
Quartus II Web Edition software removes all barriers for designing high-performance architectures and enables developers to experience the performance of the software.
Quartus II Subscription Edition and Web Edition feature comparison table.
| Feature | Quartus II Subscription Software |
Quartus II Web Edition Software |
|---|---|---|
| Licensing |
Paid license is perpetual (continues to work after expiration) Free 30-day evaluation license also available |
Free 150-day license (request another free license after expiration) |
| Device Support | All | Cyclone III, Cyclone II, Cyclone, Stratix III EP3SE50, EP3SL70 Stratix II EP2S15, Stratix EP1S10, ACEX 1K, APEX 20K EP20K30E, APEX 20K EP20K60E, APEX 20K EP20K100E, APEX 20K EP20K160E, APEX 20K EP20K200C, FLEX 10K, FLEX 10KA, FLEX 10KE EPF10K30E, FLEX 10KE EPF10K50S, FLEX 10KE EPF10K100E, FLEX 10KE EPF10K130E, FLEX 10KE EPF10K200S, FLEX 6000, MAX II, MAX 3000A, MAX 7000B, MAX 7000S, MAX 7000AE |
| MAX+PLUS II Look and Feel | Yes | Yes |
| Support for Altera and AMPPSM Partner Intellectual Property (IP), Including OpenCore Plus Evaluation Feature | Yes | Yes |
| Full License to IP Base Suite MegaCore Functions Including FIR and NCO Compilers and DDR, DDR2, QDR II, and RLDRAM II Memory Controllers | Yes | No |
| RTL Viewer and Technology Map Viewer | Yes | Yes |
| LogicLockTM Incremental Design Regions and Custom Regions | Yes | No |
| TimeQuest Timing Analyzer | Yes | Yes |
| Timing Closure Floorplan | Yes | Yes |
| Assignment Editor and I/O Pin Checking Features | Yes | Yes |
| Chip Planner | Yes | Yes |
| Netlist and Physical Synthesis Optimizations | Yes | Yes |
| Timing and Resource Optimization Advisors | Yes | Yes |
| PowerPlay Power Analysis and Optimization Tool | Yes | Yes |
| Project Archive | Yes | Yes |
| Tcl Scripting Support | Yes | Yes |
| Fast Fit | Yes | Yes |
| SignalTap II Logic Analyzer | Yes | Available if the TalkBack feature is enabled |
| SignalProbe Feature | Yes | Available if the TalkBack feature is enabled |
| STAMP Models | Yes | Yes |
| Save Intermediate Synthesis Results | Yes | Yes |
| SOPC Builder | Yes | Yes |
| Design Assistant | Yes | Yes |
| HardCopy Tools | Yes | No |
| Advanced Tutorials | Yes | No |
| Virtual I/O Pins | Yes | No |
| Device Migration | Yes | Yes |
| Enable/Disable Messages | Yes | Yes |
| IBIS Model Generation | Yes | Yes |
| FIFO Partitioner Megafunction | Yes | No |
| Testbench Generation From Vector Waveform Files (.vwf), Testbench Template Generation | Yes | Yes |
Source: Altera Quartus II
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