Quad-MAC DSP core - CEVA-X1641 - CEVA

CEVA announced the CEVA-X1641 Quad-MAC DSP core, designed to run highly computational intensive tasks that require high data throughput and memory bandwidth. CEVA-X1641 is a Quad-MAC member of the CEVA-X DSP family consisting of 16-bit data width and four MAC units. The CEVA-X1641 DSP core is fully synthesizable with enhanced memory architecture, providing developer with the flexibility to configure the optimal memory size and structure for their specific application such as WiMAX, WiBro, 3G Long Term Evolution (LTE) and H.264 compression.

CEVA-X1641 Quad-MAC DSP Core Block Diagram

Gideon Wertheizer, CEO of CEVA, said:

The CEVA-X1641 DSP core is in line with our strategy to offer platforms that will support the growing need for performance and power-efficient DSPs for emerging wireless and multimedia standards…

Our new, high-performance and fully synthesizable CEVA-X1641 DSP core will enable customers to expedite their time-to-market and reduce development costs by using the same platform across multiple, differentiated products…

CEVA-X1641 Quad-MAC DSP core is fully compliant with the CEVA-X Instruction Set Architecture (ISA). Like other ISA compliant cores, the new DSP core is a combined VLIW/SIMD architecture, with additional features and enhancements required to handle the high-performance and data-throughput requirements of 4G technologies and multimedia applications. CEVA-X1641 DSP core incorporates specialized video instructions to accelerate multimedia processing in applications like mobile TV and video conferencing.

The CEVA-X1641 DSP core provides a high-performance, low-power platform allowing its licensees to develop multi-mode products (e.g., 2G/3G/4G processors) and to reuse the same platform for next-generation standards such as 802.16e, WiBro, Flash-OFDM, UMTS and TD-SCDMA.

Target market of CEVA-X1641 Quad-MAC DSP core includes:

• 4G and WiMAX cellular handsets and Software Radio
• Video & Audio processing for mobile devices
• SmartPhones / PDAs
• Home entertainment (Digital TV, HDTV, PVR, HD-DVD)
• VoIP Gateways & broadband modems

The CEVA-X1641 Quad-MAC DSP core is upward compatible with CEVA-X1620 and CEVA-X1622 DSP cores, enabling licensees of the CEVA-X1641 to leverage the broad range of software and components already available for the CEVA-X architecture. The new core  is only 5 percent larger than its Dual- MAC predecessor, the CEVA-X1620.

Delivering on the promise of the scalable CEVA-X family introduced in 2003, the CEVA-X1641's main features are:

• Quad MAC 16-bit fixed point DSP
• Combination of VLIW and SIMD architecture concepts
• Variable instruction width (16/32-bit) and variable length of instruction packets
• Up to 8 instructions issued simultaneously
• Two level memory architecture
  • Up to 4G byte addressable memory space
  • 64K/96K/160K byte L1 program memory and cache
  • 64K/128K byte L1 data memory
  • Program and data DMAs
• All instructions can be conditionally executed
• Nine stage pipeline

High Performance at Low Power Consumption
CEVA-X1641 Quad-MAC DSP core has a unique mix of  and Single Instruction Multiple Data architectures. The Very Long Instruction Word architecture allows a high level of concurrent instructions processing thus providing extended parallelism, as well as low power consumption. Single Instruction Multiple Data allows single instructions to operate on multiple data elements resulting in code size reduction and increased performance. Low power consumption is also achieved in the CEVA-X1641 by its instructions and dedicated mechanisms.

High-level Programming
CEVA-X1641 Quad-MAC DSP architecture is compiler-driven, implementing orthogonal instruction set and operands, load/store architecture, byte addressing and simple memory configuration (no X/Y partitioning). The Computation and Bit Manipulation Unit is responsible for all DSP computations, and includes four independent functional units: Four 16×16-bit MAC units, 40-bit Shift unit and 40-bit Logical unit.

The Program Control Unit is responsible for the code flow, including sequential flow, branches, loops and interrupts. The Dispatch Unit analyses instruction packets and dispatches single instructions to the different functional units.

The Data Address and Arithmetic Unit includes two identical Load/Store Units, responsible for generating all data memory accesses. The Scalar Unit is a 32-bit integer CPU block, supporting arithmetic, shift and bit manipulation operations on 32-bit data types.

The data memory subsystem supports a user configurable size L1 memory and up to 4G byte of L2 memory, through an AHB-Lite system bus and a programmable DMA. The program memory subsystem supports a user configurable size of L1 memory, with or without a 32KB program cache. Using a separate AHB-Lite system bus and a programmable DMA, these can be extended up to 4G byte in L2.

Soft Core
CEVA-X1641 Quad-MAC DSP core implementations are Soft Core based. This feature allow developer to select the optimal operating point in terms of die size, power consumption and performance. CEVA-X1641 IP incorporates fully automated design flow supporting mainstream EDA tools, significantly shortens time-to-market. CEVA-X1641 design can be ported to an FPGA.

About CEVA, Inc.
CEVA is the licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry. CEVA licenses a family of programmable DSP cores, associated SoC system platforms and a portfolio of application platforms including multimedia, audio, Voice over Packet (VoP), Serial Attached SCSI (SAS) and Serial ATA (SATA)

More info: CEVA-X1641 Quad-MAC DSP Core