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PlanAhead 9.1 Design Suite - Xilinx

Posted in Development Tools, PLD, FPGA, ASIC,..., Xilinx
On Wednesday, March 21, 2007

Xilinx announced the new version of PlanAhead design and analysis software. The PlanAhead 9.1 offers option for designers to optimize the performance of the Xilinx 's 65nm Virtex-5 FPGAs.

PinAhead Technology using by PlanAhead 9.1, offers FPGA designers an intuitive solution of managing the interface between target FPGA and the PCB. It offers fully automatic or semi-automated assignment of I/O ports to physical Package Pins. FPGA designers can assign interface I/O groups to I/O pins by simply drag-drop.



PinAhead Technology provides an interface to analyze the design and device I/O requirements and to define an I/O pinout configuration that satisfies the needs of both the PCB and FPGA designers. It allows designers to create the port list or import the list from CSV file. By considering the data flow from PCB to FPGA die, optimal pinout configurations can be achieved quickly.

Besides Virtex-5 LX, LXT and SXT devices, PlanAhead 9.1 also supports Spartan-3 FPGAs including the I/O optimized and non-volatile Spartan-3A/3AN.

Single-user licenses of PlanAhead 9.1 is $2,495 US (Promo)

Source: Xilinx PlanAhead 9.1 Design Suite


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