The release of OVM 2.0 (Open Verification Methodology) - Mentor Graphics, Cadence

Mentor Graphics and Cadence have announced the release of OVM 2.0, new
version of the Open Verification Methodology (OVM). The OVM is based on the
IEEE
1800 SystemVerilog standard and supports design and verification engineers
developing advanced verification environments that offer higher levels of
integration and portability of Verification IP. The OVM is fully open, and
includes class library and source code that is available for download.
The methodology is non-vendor specific and is interoperable with multiple
languages and simulators. OVM 2.0 include direct support for parameterized
classes in the OVM factory and built-in debug support for TLM (Transaction-level
modeling) connections throughout the hierarchy. This new version of OVM extends
the proven sequential stimulus mechanism in the OVM with TLM interfaces.

Open Verification Methodology (OVM)

The OVM User Guide provides straightforward documentation on all aspects of
the OVM, including an extensive review of TLM for verification, guidelines for
developing reusable OVM verification components, instructions for building
verification tests, and in-depth discussions on the more advanced features of
the OVM. The guide also includes an extensive example showing how to apply these
concepts to the creation of a full hierarchical verification environment,
including tests that configure the environment and select the desired stimulus
sequences to exercise the required functionality.

About OVM (Open Verification Methodology)
The OVM is created to facilitate SystemVerilog interoperability with a
standard library and a proven methodology. This open source product is the
result of joint development between Mentor Graphics and Cadence. OVM combines
the Cadence Incisive Plan-to-Closure URM (Universal Reuse Methodology) and the
Mentor AVM (Advanced Verification Methodology), and is usable on two-thirds of
the world’s SystemVerilog simulators. The OVM will also facilitate the
development and usage of plug-and-play verification IP (VIP) written in
SystemVerilog (IEEE 1800), SystemC (IEEE 1666), and e (IEEE 1647) languages.

Resources:

• Press release of Open Verification Methodology (OVM) 2.0
  (http://www.ovmworld.org/press_release_091108.php)
• Open Verification Methodology (OVM) overview (http://www.ovmworld.org/overview.php)