New Version of JPEG 2000 Encoder IP Core, Suitable for ASIC and FPGA System - CAST
Posted in IP - Intelectual Property, ImageOn Monday, June 4, 2007
CAST announced new version of JPEG 2000 Encoder (JPEG2K-E) IP Core, which will be shipped in Q3 this year. This new version offers a major advance that improves processing and makes it significantly easier to integrate JPEG 2000 in ASIC-based or FPGA-based systems.
JPEG 2000 Encoder IP core features:
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- About twice the processing speed of the previous version, with some of the fastest processing rates available: over 100 MSamples/sec for FPGAs and over 200 MSamples/sec for ASICs.
- Expanded support for arbitrary large images, now handling frame sizes up to 4096 by 4096 pixels without tiling, ensuring efficient processing of even the largest HDTV images.
- A new rate control capability, by which image quality is maximized while maintaining a constant post-compression bit rate that satisfies a system's transmission and decoding requirements.
- Full hardware handling of both Tier-1 and Tier-2 JPEG 2000 encoding, eliminating the need to do Tier-2 encoding in software running on an additional processor.
CAST's JPEG 2000 Encoder IP core was first introduced in 2002, providing high-quality compression of still or video images using the JPEG 2000 standard (ISO/IEC 15444-1). This flexible JPEG 2000 standard offers both lossless and lossy compression, and it can achieve higher image quality with higher compression ratios (for smaller file sizes) than the ordinary JPEG standard. JPEG 2000 is not widely used for web-based images.
The JPEG 2000 Encoder IP core was developed by CAST partner Alma Technologies. It will ship in the next quarter, in synthesizable RTL for ASICs or optimized netlists for Structured ASICs and FPGAs. Implementation results for the configurable and highly-scalable core vary greatly with application demands and user customization.
Further reading: CAST JPEG 2000 Encoder IP Core
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