New Version of Cadence’s Encounter Digital IC Design Platform

Cadence announced the new version of Cadence Encounter digital IC design platform. The new version features mixed-signal design support (65nm and below), chip optimization, diagonal routing using the Encounter X Interconnect Option. The new version also support Si2's Common Power Format (CPF) 1.0, enabling low-power design.

The latest Encounter is support of the Cadence’s Si2’s CPF 1.0 based Low-Power Solution. The Cadence Low-Power Solution offers a complete flow across logic design, verification, and implementation. CPF is an industry standard format for specifying power-saving techniques throughout the design process.

Dr. Chi-Ping Hsu, Cadence, said:

We continue to make significant improvements in Encounter platform to lead the industry in advanced low power and 45/65nm designs. The latest developments allow direct benefits to most advanced IC designs…

This release packs many major breakthroughs - holistic advanced low power, design for manufacturing support, Encounter X Interconnect Option and mixed-signal design - into a single highly integrated design environment…

The new Encounter platform also provides unparalleled design for manufacturing support, yield optimization, lithography-aware routing, mixed-signal design using new bus routing capabilities, and critical path simulation using the Virtuoso UltraSim Full-chip Simulator. The platform also features new power-aware automatic macro placement capability and support for simultaneous multi-mode and multi-corner timing analysis and optimization.

The new version of Cadence Encounter is available in L, XL and GXL offerings, the new platform provides greater ease of use, shorter design time and improved performance for advanced semiconductor design.

Source: Cadence’s Encounter Digital IC Design Platform