MemMax RD Memory Scheduler for for the Synopsys DesignWare DDR2 SDRAM Protocol Controller IP - Sonics

Posted in Memory, Synopsys
On Saturday, June 2, 2007

Sonics announced the availability of MemMax RD, a new version of MemMax Memory scheduler solution optimized for the Synopsys DesignWare DDR2 SDRAM Protocol Controller IP (intellectual property). MemMax RD seamlessly connects to any Sonics SMART Interconnect solution. This allows SoC developers to rely on Sonics' multi-threaded, non-blocking flow control data flow management schemes f rom the processor through the memory scheduler.

Phil Casini, Sonics, stated:

With more than 10 years in the semiconductor intellectual property market, Sonics has observed first hand the system engineering problems that arise f rom using these ad hoc components. Often, many months of engineering trying to make these solutions work leads to system performance compromises…

By collaborating with Synopsys, we combined seamless connectivity with the state-of-the-art DDR2 controller and PHY set with the deep systems knowledge and experience we have. Sonics MemMax RD represents a truly new generation of solution…

Connecting MemMax RD Memory Scheduler to the DesignWare DDR2 SDRAM Protocol Controller IP has demonstrated greater than 5 Gigabytes/second external memory bandwidth and over 80 percent channel utilization, while satisfying the throughput and quality of service (QoS) requirements for demanding applications such as high definition video streaming.

The availability of MemMax RD Memory Scheduler comes as a result of the two companies successfully collaborating on a system on chip (SoC) SDRAM memory subsystem reference design, which outperformed a production subsystem based on a proprietary DDR2 controller design for high-definition television video streaming. SoC developers can now utilize the MemMax RD Memory Scheduler and the Synopsys DesignWare DDR2 SDRAM Protocol Controller and PHY IP components for multicore SoCs and achieve ultra-high memory bandwidth with significantly reduced engineering effort.

The emergence of multicore SoCs as a defacto standard architecture in the convergence era has dramatically complicated SoC data flow management. Among the many data flow services required, advanced arbitration schemes either inside the SoC interconnect or designed as part of the memory scheduling logic must provide QoS to satisfy the performance requirements of each processor's access to a shared external memory channel, while still achieving very-high channel utilization. The channel utilization, defined as the fraction of SDRAM clock cycles in which useful data is sent or received, determines the type, frequency, and configuration of external DRAM components that are required to achieve a given level of system performance.

Multicore SoCs require complex memory scheduling algorithms to be built into the memory subsystem to achieve the required channel utilization and QoS. Such memory schedulers choose requests f rom the different processors to exploit the bank-level parallelism of the memories and optimize in-page operations to maximize throughput, and independent scheduler ports per processor are traditionally required. The breakthrough represented with MemMax RD Memory Scheduler is its ability to use only a single multi-threaded interface featuring non-blocking flow control to enable the interconnect to multiplex the processor traffic while delivering both high channel utilization and excellent QoS. MemMax RD Memory Scheduler offers significantly lower average and worst-case latency to high-priority processor traffic and higher channel utilization than other approaches that share a single out-of-order port between the interconnect and memory controller.

MemMax RD Memory Scheduler seamlessly connects to any Sonics SMART Interconnect solution. This allows SoC developers to rely on Sonics' proven multi-threaded, non-blocking flow control data flow management schemes f rom the processor through the memory scheduler.

The DesignWare DDR2 SDRAM Protocol Controller and PHY are essential components of the reference design high-performance subsystem. The combined solution provides designers with a seamless path f rom the MemMax RD scheduler to the DDR2 SDRAM protocol controller, utilizing the maximum available DDR2 memory bandwidth. The silicon-proven DesignWare DDR2 Memory Interface IP solution is optimized for improved data bandwidth, low power and enhanced signaling features, delivering predictable memory system performance of up to 800 Mbps per bit lane and beyond.

About Sonics MemMax Memory Scheduler

The Sonics MemMax Memory Scheduler provides significant performance increases through unprecedented control and management of concurrent accesses to shared off-chip DRAM. As system-on-chip complexity grows, one of the largest roadblocks to success is costly, inefficient access to shared, off-chip memory. The Sonics MemMax Memory Scheduler provides Quality of Service (QoS) guarantees to initiator cores, drastically lowering the risk of starving high-demand initiators such as DSPs and graphics processors. MemMax is an intelligent, OCP (Open Core Protocol) compatible DRAM access scheduler designed for use in conjunction with an OCPwrapped memory controller and the Sonics SonicsMX® SMART Interconnects® solution.

MemMax Memory Scheduler offer some advantage over conventional memory controllers, such as:

Increases bandwidth utilization up to 40% while still meeting QoS requirements by using short bursts (based on simulated traffic)
Reduces power and area by allowing large centralized buffers to be implemented as compiled memory (MemMax is predominantly buffering)
Prioritizes requests f rom latency sensitive initiators, resulting in a relative decrease in latency where it is needed

Incorporating patent-pending technology, MemMax Memory Scheduler manages and schedules multi-threaded pipelined accesses to DRAM to improve memory utilization and bandwidth by up to 40%, depending upon the burst size used. Due to the intelligence added to the memory subsystem by MemMax Memory Scheduler, SOC designers can use compiled RAM to consolidate all of the flip-flop based buffers normally distributed among the various initiator cores into a single buffer within MemMax Memory Scheduler. This reduces total SOC die area and lowers overall power consumption. Instantiated with SonicsMX, MemMax Memory Scheduler significantly reduces SoC costs and time to market by eliminating a substantial amount of the excessive wire interconnects required by traditional wire-based, multi-layered bus architectures.

Ideal for existing and future high-bandwidth applications, such as data aggregation and in-home networking and entertainment, MemMax’s sophisticated thread-based pipelining and arbitration scheme brings an unmatched Quality of Service to on-chip cores while reducing interconnect over-design and redundancy. Armed with full knowledge of the number, nature and initiating source of all memory accesses, and the ability to reorder requests in accordance with the state of the DRAM, MemMax Memory Scheduler guarantees QoS, thereby reducing SOC costs by eliminating redundant banks of memory. Further, MemMax Memory Scheduler decouples the functionality of the SOC f rom the DRAM technology used, providing the flexibility to readily adopt the latest DRAM technology offering the best cost and performance value.

Benefits of MemMax Memory Scheduler includes:

Increases SOC performance
Guarantees Quality of Service for on-chip cores
Improves efficiency of off-chip DRAM by up to 40%
Lowers SOC costs
Single SMART Interconnects solution replaces multiple layered busses
Consolidates and reduces multiple distributed buffers
Shortens time to market
Accurate architectural exploration ensures functionality in first days of development
Smart Interconnect removes wire routing problem of classical architectures
Increased market penetration
DRAM technology selection decoupled f rom the rest of the SOC

The MemMax Memory Scheduler takes in multiple data flows f rom a Sonics SMX Inter-connect and schedules corresponding DRAM requests to achieve an optimum balance between the competing goals of efficient DRAM usage and Quality of Service guarantees.

This scheduling increases DRAM efficiency by re- ordering requests to take advantage of the optimum access schedule for the DRAM. Because there are no ordering requirements between threads, requests f rom different threads can be freely re-ordered. Different bandwidths and Qualities of Service (QoS) may be allocated to different threads to effectively support system data flow requirements.

To complete the shared DRAM subsystem, a DRAM controller is placed between MemMax Memory Scheduler and the shared DRAM. MemMax Memory Scheduler interfaces to both SMX and the DRAM controller using a configurable OCP interface.