Libero IDE for FPGA Design - Actel

Actel Corporation announced version 8.0 of its Libero Integrated Design Environment (IDE) for FPGA design. The new version offers SmartDesign, enabling users to design at a higher level of abstraction. The new tool suite supports all the Actel's FPGAs, including the flash-based, low-power ProASIC3 and 5 Micro Watt Actel IGLOO FPGAs, an also the single-chip Actel Fusion PSC (Programmable System Chip).

Rich Brossart, Actel, said:

Helping designers to stay within their ever-tightening power budgets, Libero excels with its accurate and easy-to-use SmartPower power analysis tools. The 8.0 enhancement to the Actel Libero tool suite represents our latest innovation aimed at easing the design and support of power-efficient applications…

Whether users are designing an ARM processor, a Fusion-based subsystem or a portable application using our low-power IGLOO devices, Libero IDE v8.0 with SmartDesign speeds the design process and provides correct by construction confidence…

The Libero’s SmartDesign lets users visually create and then automatically abstract block-based system designs into synthesis-ready VHDL or Verilog components. The graphical block-based design entry supports prefabricated blocks from Actel's extensive DirectCore and SmartGen IP libraries. It also supports custom blocks created in HDL or Synplify DSP and processor subsystems created with Actel's CoreConsole tool.

SmartDesign Block-Based System-level Design Environment
An innovative SmartDesign capability enables source file components, such as SmartGen- and CoreConsole-configured IP and processor cores, HDL modules, Actel cell macros, and Libero-created blocks, to be visually brought together onto a white-board canvas in a block-diagram view. A catalog provides an extensive list of IP, macros, HDL templates, and bus interfaces that can be selected and dragged and dropped onto the canvas. Thus, SmartDesign facilitates real design re-use and paves the way for future block capture designs using system Verilog, DSP, mixed hardware/software blocks, and more.

While capturing a design, a SmartGuide function suggests compatible bus interfaces and IP cores that may be appropriate for the design. This same function, serving as a design rule checker, ensures the connections are correct by construction. Upon completion, a synthesis-ready HDL source file is created. With many connections automatically made by the SmartConnect function within SmartDesign, the Libero IDE v8.0 enables designers to save time and minimize errors.

New Features Ease Fusion Power Management Designs
Actel's mixed-signal FPGA family, Fusion, receives additional support in Libero IDE v8.0 with the FlashPro 6.0 software update. Used with FlashPro programmers, this new version of the software further eases the programming of Actel's IGLOO/e, ProASIC3 and Actel Fusion devices. A new feature in FlashPro, called FlashPoint, increases the flexibility in design finalization by allowing the user to modify and edit the FlashROM security settings independent of Libero or Designer. This saves the user from having to re-run the design through synthesis, place and route, and program file generation, significantly reducing overall design time.

The Actel Libero IDE 8.0 Platinum for Windows and Linux platforms is priced at $2495. Actel also offers a limited feature Gold edition (Windows) for free. All editions are one-year renewable licenses.

More info: Actel Libero IDE 8.0  for FPGA design