LatticeXP2 FPGA Family featuring Instant On, Ram Backup and Enhanced Security

Lattice announced the availability of  LatticeXP2 family, its third generation non-volatile FPGAs. LatticeXP2 family is designed using the advanced non-volatile FPGA technology, a 90nm embedded Flash process co-developed with Fujitsu. The devices provide the instant-on, smaller footprint, live update capabilities, RAM back-up, and enhanced design security. LatticeXP2 FPGAs family doubles maximum logic capacity to 40K Look Up Tables (LUTs), improves performance 25% and adds dedicated DSP blocks, all while reducing the price per function by up to 50%. Power consumption has also been optimized on the 1.2-volt process technology, reducing static power usage by 33%.

Stan Kopec, Lattice Semiconductor, said:

FPGA designers have enthusiastically accepted our prior generation, the LatticeXP Flash-based FPGA family, with thousands of cumulative design-ins worldwide to date…

We're gratified that this success has attracted the attention of one of our larger competitors who has recently attempted to jump on the non-volatile bandwagon, albeit with hybrid, multi-die devices that do not deliver the full advantages of our non-volatile FPGAs. The broad array of enhancements found in our new LatticeXP2 non-volatile FPGAs, reflecting our 'More of the Best' philosophy, is the result of our ongoing dialog with designers who have used our LatticeXP devices. With enhanced features and lower prices, LatticeXP2 devices will further expand the use of non-volatile FPGA technology and accelerate the growth of this increasingly important segment of the FPGA market…

The LatticeXP2 Family
There are five members of LatticeXP2 family with capacities from 5K to 40K 4-input Look Up Tables (LUTs). Embedded block memory provides up to 885Kbits in 18Kbit dual port blocks. For small scratch pad memories, LUTs can also be converted into small blocks. The devices have up to 12 sysDSP blocks provide hardwired high-performance pipelined multiply and accumulate functions. The devices also offer up to four Phase Locked Loops (PLLs) that can be used to align and synthesize clocks.

Lattice designed the LatticeXP2 family to use a 1.2-volt core voltage for low power consumption. The circuit design was tuned to reduce static power per logic function by approximately 33% overall.

I/O capacities for the family range from 86 to 540 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of Double Data Rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400Mbps, high performance ADC/DACs at up to 750Mbps and 7:1 LVDS display interfaces at above 600Mbps.

flexiFlash Architecture
Flash memory blocks are embedded within LatticeXP2 FPGAs to store the device configuration. At power up or on user command, the data stored in the Flash memory is transferred massively into SRAM cells that control the configuration of the device. The massive transfer enabling the device logic to be available in about  1mS. This instant-on capability is critical for many system functions such as power up sequencing, address decoding and reset logic.

LatticeXP2 keep the configuration bitstream on-chip, more secure than alternative multiple chip/device module solutions. This security is enhanced by configuration read-back protection modes. A 64-bit erase/program lock protects against accidental or unauthorized device programming. A one time programmable (OTP) mode is provided for ultimate protection against unauthorized programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device.

The LatticeXP2 devices support up to 885Kbits of FlashBAK memory. This exclusive capability allows Embedded Block RAMs to be initialized at power up from Flash memory. During device operation, designers can also choose to write updated data from the block RAM back into the Flash memory. This provides a method to store data such as Power On Self Test (POST), microprocessor code and calibration data. An additional 0.6 to 3.3kbits of Flash memory is provided in the form of Serial TAG memory for general-purpose use by system designers for storage of device revision data, board identifiers and other data.

A Comprehensive Solution for Field Updates
Increasingly, electronic equipment is designed to support field updates and bug fixes. It is critical that these updates are done reliably, securely and, in many cases, without interrupting equipment operation. The LatticeXP2 devices address these three requirements. To protect against incomplete new configuration downloads due to communication or system failures during field updates, important configuration can be stored in an optional external SPI boot memory and the LatticeXP2 device can boot automatically from this configuration if bitstream errors are detected. An on chip, user defined 128-bit AES decryption key and associated circuitry allows programming data to be encrypted and securely sent to the device remotely, preventing program intercept and piracy. The devices also support
TransFR (Transparent Field Reconfiguration) technology that allows new configurations to be loaded into the LatticeXP2 device while the I/O states are precisely controlled, allowing new configurations to be applied while the overall equipment continues to operate.

A New Generation of Design Tools
Lattice is also releasing a new generation of its ispLEVER design tool suite version 7.0. This version provides major general enhancements including substantial speed and utilization improvements for all Lattice FPGA families, a greatly enhanced Power Calculator module, the entirely new Reveal design analysis tool with the industry's most advanced logic analysis triggering capabilities and many other enhancements. ispLEVER version 7.0 will be shipped by the end of June to all Lattice registered software users on maintenance contract.

Availability and Pricing
Samples of the first member of the LatticeXP2 family, the 17K LUT LatticeXP2-17, in 208PQFP, 256ftBGA and 484fpBGA packages are available now. Lattice plans to bring the entire device family to market during 2007. The LatticeXP2-17 will be priced as low as $12.00 in 100K unit quantities for delivery in 2008.

More info: LatticeXP2 FPGA Family