New ispLEVER 7.1 FPGA Design Tool features Simultaneous Switching Output (SSO) Analyzer and Multi-Processor Compilation - Lattice

Lattice’s ispLEVER 7.1 FPGA design tool suite for Windows (including Vista), Linux and UNIX users is available immediately. A number of performance-enhancing features and new functions are delivered in this new release, including the dedicated FPGA Simultaneous Switching Output (SSO) Analyzer. With the SSO Analyzer, FPGA designers will be able to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a PCB (Printed Circuit Board). ispLEVER 7.1 FPGA design tool suite now support multi-processor powered design compilation to achieve the faster timing closure. The new design tool can provide 30% faster FPGA design compile times.

New features and enhancements of ispLEVER 7.1 FPGA design tool:

• Windows Vista Support
• Interactive Synthesis Flow
• Find Module Function in Project Navigator
• Design Planner Enhancements
  • SSO Analyzer
  • Find and String Filters
  • Interactive Trace Report
  • Color Coded Port Groups and DQS Span
  • Enhanced EBR and DSP Block Information
  • Improved Pin Display Select Dialog
• Preprocessor Directives for Design Preference Files
• Reveal Logic Debugger Tool - Expanded VHDL Support
  • Boolean / Integer
  • Enumerated Data Types
• Map Place and Route (MPAR) Enhancements
  • Multi-core Processor Support for Batch Runs of Place and Route
  • Congestion Driven Routing Options
  • Guided MPAR
• Power Calculator Enhancements
  • Power Graph
  • Effective Thermal Resistance

An enhanced Power Calculator enables FPGA designers to analyze and optimize power requirements early in their design. The Lattice Power Calculator includes an exceptionally user-friendly interface that enables power analysis at the block level and examination of "what-if" scenarios by changing design environment variables.

The new ispLEVER 7.1 FPGA design tool improves post-route design operating frequency of up to 5% and runtime reductions by as much as 30% for larger designs.

The release of ispLEVER version 7.1 FPGA design tool is the first that includes the latest LatticeMico32 support. A recent release of the LatticeMico32 embedded processor solution included Linux O/S-based tools, VHDL language support (through VHDL wrappers of the Verilog IP) and added arbitration support. The ispLEVER 7.1FPGA design tool release seamlessly integrates the LatticeMico32 Mico System Builder into its design flow. The new arbitration support automatically selects the appropriate Wishbone Bus arbitration scheme when the microprocessor platform is generated, enabling shared-bus or slave-side arbitration. This capability allows multiple master ports efficient access to multiple slave ports.

Lattice also has recently added the uClinux O/S to a portfolio that already included RTOS support from Micrium and µITRON.

More info: Lattice Semiconductor