Iridix v6 Video Enhancement IP Core for Spartan-3 Platform
Posted in PLD, FPGA, ASIC,..., Favorite, Xilinx, Video, IP - Intelectual Property, TVOn Thursday, January 25, 2007
Xilinx, Inc (programmable logic supplier) and Apical (image processing solution provider), introduce the Iridix v6 video enhancement IP core for the Xilinx Spartan-3 platform. This arrangement supports higher definition 1080p displays and using only 20 percent more FPGA resources than the Iridix v5 768p core. This solution was showcased CES January 8-12, Las Vegas.
Michael Tusch, Apical, said:
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The Iridix v6 core provides breakthrough video enhancement algorithms to substantially improve the video quality of emerging 1080p HD displays…
The Apical-Xilinx solution comprises pixels dynamic range compression, fine pixel/edge preservation and color correction algorithms. The IP Core leverages BRAM (Block Ram) resources of the Spartan-3 FPGAs. The FPGA and IP solution complements existing video processing ASSPs.
Source Apical
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