Interoperability of Virtex-5 FPGA and CS3477 40 Gbps Ethernet Using Interlaken Protocol

Cortina and Xilinx announced successful interoperability of the Virtex-5 FPGA and Cortina's new CS3477 Ethernet MAC chip. The interoperability is established via Interlaken protocol, the open specification for high-speed chip-to-chip serial packet transfers. This configuration enables component manufactures to scale their devices to 40 Gbps and higher.

Per Holmberg, Xilinx, said:

Designers need maximum interconnect performance and many of our communications customers have been asking for technologies like Interlaken to break the bandwidth ceiling imposed by SPI.4…

Interlaken leverages the advanced serial transceiver technology introduced with our 65-nm Virtex-5 FPGAs last year, providing 40 Gigabits today with a runway up to 100 Gigabits or more…

Virtex-5 is built upon advanced 65nm triple-oxide technology. The Virtex-5 family is the fifth generation in the award-winning Virtex product line. Virtex-5 FPGAs consume 45 percent less area than previous generation 90nm FPGAs.

Cortina's CS3477 is 40Gbps Gigabit Ethernet MAC aggregation IC. It simplifies design with four on-board XFI serdes for direct connection to XFP optical modules and connects up using high speed Interlaken.

Source: Xilinx