IBM announced Cu-45 High Performance 45-nm ASIC Silicon On Insulator (SOI)

IBM announced its Cu-45 High Performance Custom Chip (ASIC), developed based on IBM’s 45-nm Silicon On Insulator (SOI) technology. This technology offers significant intrinsic advantages in compare to bulk CMOS-based chips, because of the decreased junction capacitance provided by the oxide layer in SOI. The Cu-45HP ASIC  offering is the the first commercial use of a new gen of embedded dynamic random access memory (eDRAM) in SOI technology.

IBM 45-nm SOI PFETs (Cross-section)

Tom Reeves, IBM GES Semiconductors and Services, stated:

The market can now take advantage of chip products that harness IBM's leadership in research and innovation…

From the first ASIC SOI chip at 45nm to the use of the new eDRAM and chip integration technologies, the advances that are part of these new semiconductor offerings enable flexible, cost-effective products that enhance the value of customized IBM semiconductor solutions…

SOI technology has been part of six generations of Power Architecture processors in IBM server products. It provides up to a 30 percent performance boost compared with industry standard complementary metal-oxide (CMOS) technology. The new 45nm eDRAM technology implemented in SOI can dramatically improve on-processor memory performance in about one-third the space with one-fifth the standby power of conventional SRAM (static random access memory).

Features of Cu-45HP:

• Dual logic oxide technology, with 12-angstrom logic devices for significant performance advantages and 16-angstrom logic devices for substantial leakage current benefits
• Support for both 9-track and 12-track design libraries for density or performance advantage, respectively
• Multiple Vt design libraries for power and performance trade-offs (high, regular and low Vt, with the high Vt design library offering the lowest leakage and the low Vt design library offering the highest performance)
• Up to a five times reduction in the soft error rate (SER) because the well area between the drain and source of the transistors in SOI is smaller than that of bulk CMOS devices
• Flip-chip plastic ball grid array (PBGA), electrically-enhanced PBGA and thermally- and electrically-enhanced PBGA package options (planned); custom package offerings possible

Key specifications of Cu-45HP

• Technology: SOI
• Process generation: 45nm
• Gate delay: 3.8–9.9 ps
• Wireable gates: 200 millions
• Raw circuit density: 1480 Kgates/mm2
• Transistor leakage: 0.2-50 nA/μm
• Total levels of metal: 9-10
• Power dissipation: 3.2/2.6 nW/MHz/gate
• Thin-level dielectric: Ultra low-k
• Supply voltage VDD: 1.0/0.9 V

IBM also announced three additional digital and analog IBM semiconductor product offerings targeting mobile handsets and other wireless products — including the capability to further on-chip integration for improved cost, performance and density:

• SiGe BiCMOS 5PAe - this silicon germanium-based analog offering is the first-ever IBM product based on the IBM through-silicon via technology and can lower costs for clients who are designing power amplifiers for cell phones, wireless phones and WLAN/WiMAX applications.
• SiGe BiCMOS 6WL technology - a cost-optimized version of existing IBM technology aimed at bringing value to clients demanding high performance analog for high-volume consumer applications including mobile phones, WLAN, and global positioning devices.
• CMOS 11LP - optimized for lower device leakage for handset design, the offering includes performance and low leakage SRAM, two standard cell libraries, and is built on state-of-the-art immersion photolithography technology.

IBM SiGe BiCMOS 6WL design kits are available now. IBM plans to have SiGe BiCMOS 5PAe design kits available this summer and first design kits for CMOS 11LP Foundry products later in 2007. The planned availability date for Cu-45HP ASIC is in early 2008.

Further reading: IBM Cu-45H ASIC Silicon On Insulator (SOI)