HiPer Silicon v12. Design Tool - Tanner EDA

Tanner EDA introduced the new version of HiPer Silicon, a Windows based design suite, including schematic capture, analog SPICE simulation and physical layout.

The beta version of HiPer Silicon v12.6 will be available for preview at the DAC Conference, June 4 to 7, 2007 in San Diego.

The new S-Edit Schematic Capture includes new connection hotspot on pins and ports making wiring and current probing quicker and easier. Multiple pages schematics allow straightforward creation and organization of large complex schematics. Rendering and editing performance has been greatly improved, especially on schematics with large number of symbols. SPICE export now features faster export and simpler SPICE output specifications. Probing of small signal parameters can now be done for devices modeled as subcircuits.

L-Edit Physical layout can now stretch instances and arrays automatically adjusting their repeat counts. T-Cells can be configured to be stretchable which modifies the stretch parameters by the stretch amount and then regenerates the T-Cell. Enhancements have been added for automatic guard ring generation by using objects, wires, polygons, or boxes to designate the path of the ring.

T-Spice Analog SPICE simulation has been enhanced with multi-threaded support for faster runtimes, with added support for the RPI Amorphous-Si and Poly-Si TFT models. All Philips models (MOS9, MOS11, MEXTRAM, PSP and others) have been updated to the latest v2.4 release. Transient analysis performance improvements for faster runtimes and shorter design cycles are also included. Polynomial controlled source devices have been extended to 6th order and enhanced with new options for limiting and modifying the output currents of voltages.

HiPer Verify is now able to perform antenna rules checks including NET AREA RATIO, NET AREA, NET AREA RATIO PRINT, and incremental connectivity extraction (DRC INCREMENTAL CONNECT & DISCONNECT). Significant performance improvements have been made, in some cases up to 10x faster than previous versions especially in designs dominated by large arrays. Calibre compatibility has been enhanced with support for opposite extended measurement metric, CMACR/DMACRO, ORNET, and SHIFT.

Further reading: Tanner EDA - HiPer Silicon v12.Design Tool