HAPS-51T High-performance ASIC Prototyping System - Synopsys

Synopsys has introduced the HAPS-51T, a new addition to the High-performance ASIC Prototyping System (HAPS) product family. HAPS-51T ASIC Prototyping System is powered by Xilinx’s Virtex-5 LX330T devices, and it is an ideal prototyping system for applications using high-speed serial interfaces like Gigabit Ethernet, SATA, and PCI Express.

Synopsys HAPS-51T High-performance ASIC Prototyping System - Board

About High-performance ASIC Prototyping System (HAPS)
The HAPS (High-performance ASIC Prototyping System) solution is a high performance and high- capacity FPGA-based system for ASIC prototyping and emulation. The HAPS solution is a modular system, with multi-FPGA motherboards and standard or custom-made daughter boards, which can be stacked together in a variety of ways. Among the functions available on standard daughter boards are video processing, various memory types, and interfaces to Ethernet, USB and PCI Express.

The HAPS-51T utilizes the LX330T device’s 24 RocketIO GTP transceivers, adding on-board DDR2 memory and the new HapsTrak high-speed daughterboard connectivity scheme in a compact form factor. These features enable HAPS-51T to deliver a significant advantage in performance and versatility.

Synopsys HAPS-51T High-performance ASIC Prototyping System - On Board Functions

• 1 Xilinx Virtex-5 LX330T device in an FF1738 package
  • 2 million ASIC gates on one HAPS-51T board
• 24 RocketIO channels in 3 HapsTrak MGB connectors
  • Signaling rate: up to 3.75 Gbps
  • 12 differential clock inputs
• 476 I/O signals in 5 HapsTrak II connectors
  • Signaling rate: 1 Gbps LVDS, 600 Mbps single-ended
  • Two of the connectors are especially suited for creating a global bus between multiple motherboards
  • 32 local clocks – differential or single-ended
• 30 I/O signals in the HapsTrak MGB connectors
• 32 I/O signals for SelectMAP configuration
• 10 GPIOs in a 14-pin 2 mm header
• On-board memory
  • DDR2 SDRAM: 128M x 64 bit (can be upgraded to: 512M x 64 bit)
  • Synchronous SRAM: 2M x 36 bit
  • Flash PROM: 32M x 16 bit
• 2 pair of differential clocks + 2 single ended
• One on-board programmable clock generator
• 3 VCCO regions
  • Each region can individually be set to: 3.3, 2.5 or 1.8 V
  • 1.2 V and 1.5 V via bottom side HapsTrak II connectors
• Configuration via JTAG, on-board Flash PROM, SelectMAP or optionally from a CompactFlash card
• On-board temperature and voltage watchdog
• Temperature controlled fan driver
• Built-in self-test suite
• Battery backed-up encryption key
• Single 5V supply voltage
• HapsTrak I & II compatible

The tight connection between the Virtex-5 LX330T FPGA and the on-board memory enables flexible, high-speed memory access to satisfy even demanding communication applications. As with all HAPS systems, the HAPS-51T utilizes the HapsTrak standard, a set of guidelines for pinout and mechanical characteristics to help ensure compatibility with previous and future generations of HAPS motherboards and daughterboards. In addition, the HAPS-51T introduces the new HapsTrak MGB multi-gigabit SERDES bus with up to 8 lanes.

Full production of the HAPS-51T High-performance ASIC Prototyping System is expected to begin at the end of June this year.

More information about HAPS-51T High-performance ASIC Prototyping System can be found at http://www.synplicity.com/products/haps/