Gigabit Ethernet, PCI Express, XAUI, SONET and OC-48 Protocols for Virtex-5 FPGAs - Xilinx
Posted in PLD, FPGA, ASIC,..., Xilinx, IP - Intelectual PropertyOn Wednesday, March 7, 2007
Xilinx released Gigabit Ethernet, PCI Express, XAUI, SONET, OC-48/SDH STM-16 and Common Public Radio Interface (CPRI) protocols for company’s 65nm Virtex-5 FPGAs. Each standard protocol pack includes protocol specific physical layer characterization reports, interoperability and compliance reports, intellectual property (IP) cores and documentation.
Here is list of Xilinx of new protocol packs:
|
| Tech. | Target Markets | Application |
|---|---|---|
| PCI Express | Networking, Server and Storage | On-board control plane, Plug-in cards and Chip-to-Chip |
| Gigabit Ethernet | Server, Storage, Networking, Embedded | LAN, SAN |
| XAUI | Networking &Communications | Fabric interface chips (FIC) & Back-plane |
| OC-48/STM-16 | Networking &Communications | MAN & WAN |
| CPRI | Wireless | Base Stations |
About Virtex-5 FPGAs
Xilinx Virtex-5 FPGAs is built upon 65nm triple-oxide technology, breakthrough new ExpressFabric technology and proven ASMBL architecture, the Virtex-5 family represents the fifth generation in Virtex product line.
Each protocol pack provides interoperability certification data of the solution, ensuring compliance with a standard’s specifications. Here you can freely download the Xilinx protocol packs.
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