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FPGA-based ASIC and ASSP Verification Software - Identify Pro - Synplicity

Posted in Development Tools, PLD, FPGA, ASIC,...
On Saturday, May 26, 2007

Synplicity announced the Identify Pro ASIC and ASSP verification solution, providing designers with full visibility into FPGA-based ASIC and ASSP prototypes. Identify Pro verification software improves the productivity of existing verification methodologies, such as assertion-based verification and simulation, enabling engineer to find, fix and verify functional errors at speeds approaching that of the final device.

Juergen Jaeger, Synplicity, stated:

Identify Pro ushers in a new era of hardware-assisted verification and it is one of the cornerstones of our ASIC and ASSP verification strategy…



As ASICs become bigger, more costly and more software-centric, it is critical for the design team to be able to effectively detect and analyze bugs that otherwise would be missed until final silicon. The Identify Pro software reduces this risk significantly by giving designers full visibility into their design running at hardware speed in an FPGA-based prototype. In case of an assertion, or other trigger, the design, together with an automatically generated test bench, is uploaded into a simulator for detailed debug and analysis. By combining the visibility of a simulator with the speed of hardware, the Identify Pro software provides a true breakthrough in ASIC verification…

Working with Synopsys' VCS and other popular simulation tools, the Identify Pro ASIC and ASSP Verification Solution automatically and seamlessly connects the prototype hardware with an existing software simulation environment for comprehensive RTL code analysis and debug. The Identify Pro ASIC and ASSP Verification software provides initialization of the simulator and automatically creates a test bench from the actual stimulus of the FPGA-based prototype.

Synplicity and Synopsys announced (May 24, 2007) the signing of a joint marketing agreement intended to improve verification flows for their mutual customers. Under terms of the agreement, the companies intend to work together on next-generation , high-performance verification solutions for ASIC designers. Targeting FPGA-based prototyping environments, Synopsys and Synplicity plan to demonstrate Synopsys’ VCS ® functional verification solution working seamlessly with Synplicity’s new Identify® Pro software with TotalRecall ™ technology, a tool adding full visibility to FPGA-based prototyping systems. A press release announcing Synplicity’s Identify Pro software was distributed today (Synplicity Delivers Breakthrough ASIC Verification Solution).

Synplicity and Synopsys will be exhibiting at the 2007 Design Automation Conference, June 4-7 in San Diego, California. Synopsys will be in booth # 5278. Synplicity will be in booth # 4278 and plans a demonstration of the Synplicity-Synopsys integrated ASIC prototype flow.

The Identify Pro ASIC and ASSP Verification software enables ASIC and ASSP designers to debug the design at hardware speed, directly in their RTL source code. This allows functional verification for RTL designs that is up to 10,000 times faster than RTL simulators and enables the use of real-world stimulus. This feature is an ideal solution for verification of applications such as video, audio and networking. Used in conjunction with Synplicity's Synplify Premier physical synthesis tool, the Identify Pro software enables assertion synthesis into hardware and assertion debug.

The Identify Pro ASIC and ASSP Verification Solution offers the fastest method of finding errors in an FPGA or ASIC prototype by using live stimulus to quickly reach a trigger condition such as a functional bug or assertion failure. Once a functional bug or assertion failure is found, the Identify Pro tool's TotalRecall technology is used to initialize a standard software simulator with all signal and state values at a user-defined number of clock cycles prior to the trigger being reached. The complete module state, along with a test bench, is automatically exported to an RTL simulator where the user can replay the sequence and diagnose bugs in the original RTL source code.

The Identify Pro ASIC and ASSP Verification software with TotalRecall technology is scheduled to be available in Q3 this year. Prices range from US$34,500 (one-year license) to US$69,000 (perpetual, floating license).

Further reading: Synplicity Identify Pro ASIC and ASSP Verification Solution


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