Four EDA Industry Leaders Support MIPS32 74K Core Family - MIPS Technologies

MIPS Technologies announced that four EDA industry leaders, Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys, Inc. will team with the MIPS to provide EDA software and tools support for its new MIPS32 74K core family. The MIPS32 74K is next-gen processor core family based on an innovative embedded micro-architecture. Long-time MIPS licensee Broadcom Corporation was the first to license the 74K core in January as an early access customer, as the company continues to drive next-generation solutions for the business, consumer and service provider markets. The MIPS32 74K cores are the fully synthesizable 32-bit processors to achieve operating frequencies greater than 1 GHz in TSMC 65nm process technology.

The MIPS 74K core is based on embedded microarchitecture, delivering  enhanced DSP capabilities.  The MIPS-Verified 74K cores are designed for high-volume applications throughout the digital and connected home, including DTV, set-top boxes, next-generation DVD players/recorders, broadband access, PON, residential gateways and VoIP, all markets where MIPS holds a commanding position. The 74K core family is designed to work with generic standard cells, memories and EDA design flows without the need for premium physical IP or costly structured logic and custom design flows. The processor family is optimized to deliver exceptional performance levels as well as area- and power-efficiencies required for today's complex SoC designs.

Jack Browne, MIPS Technologies, said:

This is great news for our customers. Not only does our go-to-market strategy for the 74K core continue to include MIPS robust ecosystem of standard tools, software and hardware, but our customers can be assured of rapid, reliable and first-rate industry support for their SoC design initiatives…

We’re delighted to align with our partners to offer an enhanced level of support with best-in-class EDA solutions optimized for our industry-leading 74K cores…

MIPS32 74K core family is designed to work with generic standard cells, memories and back-end EDA design flows. This ensures a cost-effective implementation and a fast time-to-market, especially when compared to existing solutions that require the use of premium physical IP or costly structured logic and semi-custom design flows. EDA solutions providers, including Cadence, Magma, Mentor and Synopsys, offer a complete suite of back-end design tools that allows SoC developers to rapidly implement physical designs and validate the correctness of each implementation.

Innovative Microarchitecture: Optimized for Enhanced Performance
MIPS Technologies has optimized the MIPS32 74K processor cores for breakthrough performance and area- and power-efficiencies by designing an advanced microarchitecture for the embedded market. This revolutionary core technology is compatible with the software and system interfaces of the industry-standard 24K, 24KE and 34K processors, enabling SoC designers to take advantage of their existing hardware infrastructure.

Advanced Pipeline Design Maximizes Frequency, Architecture Performance
Compared to traditional approaches, the MIPS32 74K core's 17-stage pipeline employing a unique combination of out-of-order dispatch and asymmetric dual-issue, enables a higher frequency, higher performance solution, with lower area and power. Out-of-order instruction dispatch enables the MIPS32 74K core to execute multiple instructions more often than an in-order processor,  resulting in significantly improved performance and efficiency, even for existing binary code. The ability to efficiently execute existing binaries, combined with the use of the same system interface from previous MIPS' processor cores, allows the MIPS32 74K core family to offer a seamless upgrade.

Enhanced DSP Features Help Accelerate Performance
The MIPS32 74K cores also feature enhanced DSP instructions that accelerate performance, reduce power consumption and add more signal processing functionality into the processor. Additional DSP instructions in Revision 2 of the MIPS DSP ASE eliminate the need for a separate DSP core for many audio, video and VoIP applications, reducing silicon area, system costs and design cycles.

Key Feature of MIPS32 74K Core:

• High Performance Floating Point Unit
  • Two pipelines support asymmetric dual-issue
• Advanced Branch Prediction
  • Three 256-entry Branch History Tables
  • 8-entry Return Prediction Stack
• Support for L2 Cache, including the MIPS SOC-it L2 Cache Controller
• Extensive Clock Gating for low power: Fine Grain, Block Level, Top Level

MIPS32 74K Core Product Specifications1 (Speed-Optimized)

• Speed (worst case): 1.04 GHz
• Core Area (mm2): 1.7
• Total Area (mm2): 2.5
• Performance: 1.8 DMIPS/MHz
• Power: 0.76 mW/MHz
• Process TSMC 65 nm GP
• Cache Size (inst/data): 32K/32K

More info: MIPS Technologies - MIPS32 74K Core