Feature Rich Multi-Service Processors – PMC-Sierra MSP8110 and MSP8120

Posted in Embedded Ethernet, Favorite, Internet, Networking, Security, USB
On Tuesday, September 18, 2007

PMC-Sierra has released the MSP8110 and MSP8120 Multi-Service Processors. Those two integrated SoC solutions are based on MIPS32 34K core, targeted at cost-sensitive, feature rich embedded system applications. MSP8110 and MSP8120 Multi-Service Processors are designed to meet the needs of networking appliance, network attached storage applications and embedded systems. The MSP8120 also integrates standards-based security hardware to accelerate internet protocol security (IPSec) and secure socket layer (SSL) performance.

About PMC-Sierra's MSP Family of SoC Processors
PMC-Sierra's MIPS-based SoC architecture is designed to be software compatible with the company's "RM" family of SysAD-based standalone microprocessors, giving customers the ability to increase integration and lower costs as systems enter high volume production. Designed for laser printers, networking, storage, industrial control and high-end consumer applications, PMC-Sierra's RM5200, RM7000 and RM7900 families of 64-bit MIPS-based processors provide the highest levels of processing power with low power dissipation. PMC-Sierra's MSP8100 family of highly integrated MIPS-based processors forms the foundation for future products that will provide greater processing power through high-performance I/O interconnects designed for networking appliances, storage systems and security solutions.

Network Processor

PMC-Sierra MSP8120 Processor in a Network Application

The MSP8110 and MSP8120 are part of the MSP8100 Series of feature-rich and highly-integrated products that incorporate the MIPS 34K core. The processor provides ROM, Flash, DDR, dual Ethernet, PCI, and low-speed peripheral interfaces.

 

MSP8110 and MSP8120 Multi-Service Processors support the following interfaces:

  • Two 10/100 Mb/s Ethernet MAC interfaces supporting industry standard MII/RMII interfaces to standard Ethernet transceivers
  • A 32-bit PCI controller providing PCI 2.3 compliant operation at 33/66 MHz
  • A USB 2.0 controller and PHY supporting both host and device mode operation
  • A 166 MHz DDR I/II SDRAM controller
  • Up to twenty GPIO pins that can optionally be configured as UART, SPI, TDM, or TWI ports
  • A local bus interface providing connectivity to boot ROM and Flash

In addition, the MSP8120 processor features an integrated IPSec hardware acceleration engine that boosts Internet protocol security, and provides secure socket layer performance for security appliances, firewalls, networking, and storage applications.

The MSP8120 also features an integrated IPSec hardware acceleration engine that boosts Internet protocol security, and provides secure socket layer performance for security appliances, networking, storage, and firewalls applications.


MSP8120 Processor

PMC-Sierra MSP8120 Block Diagram

Feature summary of MSP8110 and the MSP8120 Multi-Service Processors:

  • PROGRAMMABLE MEMORY MANAGEMENT UNIT
    • 8-entry Instruction TLB (ITLB) and Data TLB (DTLB)
    • 32 dual-entry Joint TLB (JTLB)
    • JTLBs are sharable under software control
  • INTEGRATED SECURITY SUBSYSTEM (MSP8120 only)
    • Dedicated 2-channel DMA controller for security packet processing
    • IPSec engine:
      • Supports all IPSec packet transforms and implements SSL packet transforms
      • Implements DES/3DES/AES crypto and SHA-1/MD-5 hash algorithm support
    • Random number generator
    • Integrated queue manager for intelligent buffer management
  • CLOCK MANAGER AND BOOT CONTROLLER
    • In single crystal mode, all on-chip clocks are generated from a single 36 MHz crystal
  • HIGH PERFORMANCE MULTI-SERVICE BUS (MS BUS) ARCHITECTURE
    • 32 bits at 166 MHz (5.33 Gbit/s)
    • DMA engines integrated for the Ethernet MACs, USB, TDM interface, security engine, and block copy engine
  • SYSTEM LOGIC AND PERIPHERALS MODULE
    • Configurable external Local Bus interface that supports data transfers up to 25 Mbytes per second
    • 3.3 V PCI Local Bus 2.3-compliant host interface
    • Clock manager and boot controller
    • Glueless interface to x8 Flash memories
    • Serial Peripheral Interface/ Microprocessor Peripheral Interface (SPI/MPI)
    • 20 GPIO pins
    • Two-Wire serial interface
    • Two external timers / clock generator
    • System interrupt controller (internal and external interrupts)
    • Two universal asynchronous serial (UART) interfaces
  • SYSTEM INTERRUPT CONTROLLER
    • Handles interrupts for on-chip peripherals and 8 external interrupts
    • Supports up to 32 PCI message signaled interrupts (MSI)
  • ETHERNET INTERFACE
    • Two independent 10/100 Ethernet MAC controllers
    • User selectable Media-Independent Interface (MII) or RMII (Reduced MII) Interface on each MAC
  • USB 2.0 CONTROLLER AND PHY
    • Both host and device mode of operation
    • Supports low-speed (LS) operation (1.5 Mbit/s), full-speed (FS) operation (12 Mbit/s) and hi-speed (HS) operation (480 Mbit/s)

In general, PMC-Sierra’s MSP8100 family of processors is supported by the Linux ecosystem of development tools available as a software development kit. This packaged system (PM2429-KIT) provides a recent Linux kernel, compiler, debugger, kernel tracer, root file system, and performance analysis tool. The kit also includes Openswan, IPSec VPN gateway and full-featured SSL OpenVPN server reference implementations.

More info: PMC-Sierra MSP8110 and MSP8120 Multi-Service Processors


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