ETSerdes Embedded SerDes Test Solution - LogicVision

LogicVision introduced the ETSerdes, a new release of  its Embedded SerDes test solution. The new release provides more accurate measurements and the ability to perform BERT (bit error rate testing). ETSerdes help developers cope with the cost and challenges of testing high-speed, multi-channel  serial I/Os.

Farhad Hayat, LogicVision, said:

As the industry adopts multi-lane, higher-speed serial I/Os, there's a need for cost-effective test strategies that scale with device performance and complexities…

…The latest enhancements to ETSerdes accommodate the increasing levels and types of noise on today’s nanometer ICs and deliver more test capabilities for reuse in the end-application.

High-speed data serialization/de-serialization I/O technologies, typically known as SerDes, are being rapidly adopted in telecommunications, data storage, and personal computer applications because they offer low power, reliable, high data-bandwidth capability using low-cost backplane and connector technologies. Significant test challenges have emerged as multiple SerDes transceivers, with data rates of up to 10 Gbps (gigabits per second), are being integrated into SOCs. As a result, IC manufacturers are finding it increasingly expensive and time-consuming to guarantee the critical signal-integrity parameters of these high speed I/Os.

ETSerdes provides unique capabilities for testing ICs with any number of high-speed serial data channels operating at any frequency, from less than 1 Gbps to more than 10 Gbps. ETSerdes provides test accuracy comparable to that of the highest performance external equipment at a fraction of the cost and is compatible with any ATE platform. The ability of ETSerdes to diagnostically measure wave shape, jitter, and jitter tolerance parameters, each in millisecond test times, can drastically reduce test costs and improve quality.

The previous release of ETSerdes IP rejected asynchronous noise from its delay measurements by averaging out the noise; the latest release is enhanced to also reject synchronous noise (which can not be reduced by averaging). This enhancement ensures that the many clock-related noise sources on-chip, especially from pin signals switching at or below the data's parallel-rate, have minimal impact on the picosecond delay measurement accuracy of ETSerdes.

LogicVision’s ETSerdes now includes an industry-standard BERT that can be controlled and monitored via a JTAG port or on-chip system signals. The BERT generates and receives a standard 7-bit based, pseudo-random bit sequence (PRBS7), or a customer-chosen PRBS, to functionally corroborate and extend the existing sub-picosecond resolution jitter and jitter tolerance tests. This embedded capability provides a typically mandatory system-level function, with system and test bus access, and includes automated test generation for quantifying signal path bit error rate (BER).

LogicVision’s ETSerdes version 6.0a is in full production and available immediately.

About LogicVision Inc.
LogicVision (NASDAQ: LGVN) provides proprietary technologies for embedded test and yield learning that enable more efficient manufacturing test of complex semiconductors. LogicVision's embedded test solutions allow integrated circuit designers to embed test functionality into a semiconductor design that is used during semiconductor production test and throughout the useful life of the chip. The company's advanced Design for Test (DFT) product line, ETCreate, works together with ETDiagnostic applications and Yield Insight to improve profit margins by reducing device field returns and test costs, accelerating silicon bring-up times and shortening both time to market and time to yield.

More info: LogicVision ETSerdes Embedded SerDes Test Solution