Enhance Reference Methodology (iRM) for ARM1176JZF-S Synthesizable Microprocessor - Synopsys and ARM

Synopsys and ARM announced an enhanced implementation Reference Methodology (iRM) for the ARM1176JZF-S synthesizable microprocessor, enabling rapid high performance and small power consumption applications. The enhanced reference methodology uses the Synopsys’s Galaxy Design Platform. It includes IC Compiler and Design Compiler topographical technology, to harness these advanced power-management techniques and provide a comprehensive implementation solution.

Antun Domic, Synopsys, said:

We knew that undertaking a project like this meant collaborating on the early science, aligning product development roadmaps and integrating the individual low-power products from both companies into a single deployable solution…

By building real silicon-based systems, we are well-positioned to understand and address the challenges faced by our mutual customers in their efforts to build low-power products and get them to market quickly. The collaboration results that serve as the basis for this RM enable designers to quickly employ aggressive power-management techniques for the ARM1176JZF-S processor are also captured in the ‘Low Power Methodology Manual…

The ARM1176JZF-S synthesizable microprocessor is widely used in a broad range of market segments, including networking, entertainment, consumer, imaging and wireless. The low-power design is enhanced with support for ARM's Intelligent Energy Manager (IEM) technology and various low-power modes. These low-power modes allow full use to be made of the leakage mitigation techniques supported in the  enhanced reference methodology, including MTCMOS power gating with state retention as well as multi-threshold voltage optimization. Combined with the enhanced iRM, IEM enables dynamic power-reduction techniques such as dynamic voltage and frequency scaling with multi-corner, multi-mode optimization.

Graham Budd, ARM, stated:

This methodology was developed as part of the ongoing ARM and Synopsys Technology Partnership…

The initial phase of the project delivered a comprehensive technology demonstrator including fully functional silicon, boards, operating system and application code. This project evaluated a wide variety of different leakage mitigation techniques and the best practices from this research were captured in the updated iRM for the ARM1176JZF-S processor. This iRM enables our customers to easily implement the most effective power-reduction techniques using the ARM1176JZF-S processor and Synopsys solutions in the process technology of their choice…

The  enhanced reference methodology can be ported to any process and standard cell library with the required low-power library components. It has been developed with ARM Advantage memories and standard cell libraries, including the Power Management Kit (PMK), part of ARM's family of Artisan physical IP, which provides a comprehensive collection of low-power library cells.

The enhanced implementation Reference Methodology will be available to ARM1176JZF-S processor licensees from ARM in Q3 of 2007

ARM and Synopsys products will be showcased at the Design Automation Conference (DAC) to be held in San Diego, CA, June 4 - 8, 2007.

Source: ARM - Enhance Reference Methodology for ARM1176JZF-S Processor