Dual-Core SuperH Microcontrollers for General Purpose Applications - Renesas

Renesas announced five new multi-core  SuperH 32-bit microcontrollers. The SH7205 and SH7265 microcontrollers use two superscalar SH2A-FPU CPU cores and on-chip peripherals including ATAPI, USB, and image processing engine. Each CPU core is able to delivers up to 480-MIPS processing speed (Dhrystone v1.1 benchmark) and  up to 400-MFLOPS floating-point operation performance.

Renesas’s multiple cores microcontrollers drastically increase the performance because those cores can execute code in parallel. The multi-core microcontrollers mostly have been aimed at multimedia products with heavy processing loads. By contrast, the Renesas’s SH7205 and SH7265 microcontrollers are general-purpose devices that target a broad span of applications requiring high-speed real-time control and processing performance equivalent to that of a DSP chip.

Renesas’ Dual Core SuperH 32-bit Microcontroller

The multi-core architecture microcontrollers makes it possible to achieve high levels of performance and  flexibility of use. The real-time processing performance does not degrade as processing becomes more complex and faster. The three main technologies in the CPU core's design are:

• The internal bus system uses a CPU-specific multi-layer structure. A 4-layer configuration provides two layers for CPU use and two for DMA Controller use. This prevents time from being wasted while the bus is in use by the other CPU, for high-speed real-time processing.
• The CPU cores can operate on different operating systems or the same one. If one CPU core runs the µITRON OS, while the other runs the µClinux OS, for example, they can execute completely different programs.
• The two CPU cores can communicate directly with each other. Each CPU can check the status of the other one, and they can exchange data using memory provided for that purpose.

The built in peripheral functions of the SH7205 and SH7265 chips reduces the need for external parts. The peripherals  include ATAPI interface, USB v2.0 (High-Speed) specification interface and other various interfaces. The devices have a 2D graphic engine and a digital video input pin for graphic processing. The graphic engine also has QVA-size (320×240-pixel) and WQVA-size (480×234-pixel) analog RGB output pins for image and video output processing.

Other on-chip functions include a 5-channel multifunction timer unit (MTU) suitable for motor control systems, 2-channel CAN controller, 8-channel 10-bit A/D converter, 2-channel 8-bit D/A converter, watchdog timer (WDT), 14-channel DMAC with 2-dimensional addressing capability for speeding up video applications, and more.

The SH7265 also provides an encoding accelerator for Advanced Audio Coding (AAC) as the audio data compression method. This function can be used for high-speed hardware implementation of music data or similar AAC file creation.

For development, engineer can use the available assembler, compiler and linker products for the SH7205 and SH7265 microcontrollers. Renesas is also developing the µITRON HI7200/MP, an enhanced version of the E10A-USB emulator with dual-core operating system. This operating system has an inter-CPU communication function and enables the software resources to be used in dual-operating system operation.

Source: Dual-Core SuperH Microcontrollers - Renesas