Development Kit for TI’s TMS320DM6446 DaVinci Digital Media SoC - Empower LDK6446

Posted in Development Tools, Multimedia, Texas Instruments
On Tuesday, August 21, 2007

Empower Technologies has released its LDK6446 Development Kit for TI’s DM6446 DaVinci dual-core TMS320DM6446 Digital Media SoC. The LDK6446 comes with the latest LEOs operating software and Software Development Kit. The hardware includes a DM6446 evaluation board and a 4.3" WQVGA LCD (480×270) touch panel screen. Empower is also going to release the LDK6441 and LDK6443 development kits for DM6441 and DM6443 respectively.

LDK644x development kits are designed specifically for media devices in the mobile, set-top-box, and telematic applications. The video processing power enabled by the TMS320C64x+ DSP onboard in the DM644x provides major technical advantages in video encoding/decoding, video analytic, audio encoding/decoding and sound processing. Those technical advantages can be applied in the fields of wired/wireless media streaming, security surveillance, portable navigation, automobile infotainment, and video telephony.

Price of LDK6446 development kit is US$1,800

About DM6446
The DM6446 has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two…
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2…
The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

About Empower Technologies
Empower Technologies (TSX.V: EPT) is an innovative company that brings the power and flexibility of the LEOs (LinuxDA Embedded Operating System) to the dynamic embedded computing Industry and the emerging Intelligent Appliance Market, through their development of Linux-based operating software, embedded system technologies and solutions. The products and services that form the base of its business activities include an embedded system development platform for LEOs, based on Texas Instruments embedded CPU platform, that fulfill the needs and demands of developers and the embedded computing Industry. Empower is continuing to develop LEOs and newer versions of embedded CPUs in line with Texas Instruments…

More info: Empower LDK6446 Development Kit for DM6446 DaVinci Digital Media SoC

DM6446 Davinci Digital Media SoC

The TMS320DM6446 (or simply DM6446) Digital Media SoC, leverages TI’s Davinci technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. The DM6446 feature robust operating systems support, high processing performance, rich user interfaces, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

TI’s TMS320DM6446 Digital Media SoC

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an ARM926EJ-S MPU core.

Key properties of DM6446 Digital Media SoC:

CPU	1 C64x+; 1 ARM9; DaVinci Video
Peak MMACS	4752
RISC Frequency(MHz)	297
Frequency(MHz)	594
On-Chip L1/SRAM	112 KB (DSP),40 KB (ARM)
On-Chip L2/SRAM	64 KB (DSP)
ROM	16 KB (ARM)
EMIF	1 16/8-Bit EMIFA,1 32/16-Bit DDR2
External Memory Type Supported	Async SRAM,DDR2 SDRAM,NAND Flash,SmartMedia/xD
DMA	64-Ch EDMA
Video Port (Configurable)	1 Dedicated Output,1 Dedicated Input
Hardware Accelerators	Resizer,OSD,Previewer,H3A,VICP
EMAC	10/100
HPI	1 16-bit
MMC/SD	1
ATA/CF	1
ASP	1
I2C	1
SPI	1
UART	3
VLYNQ	1
USB	1
PWM	3
Timers	2 64-Bit GP,1 64-Bit WD
Core Supply (Volts)	1.2 V
IO Supply (Volts)	1.8 V,3.3 V
Operating Temperature Range (°C)	0 to 85

TI’s DM6446/DM6443 Digital Media SoC Block Diagram

Key features of DM6446 Digital Media SoC:

High-Performance Digital Media SoC
- 594-MHz C64x+™ Clock Rate
- 297-MHz ARM926EJ-S™ Clock Rate
- 4752 C64x+ MIPS
- Eight 32-Bit C64x+ Instructions/Cycle
- Fully Software-Compatible With C64x /ARM9™
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
  - Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Operation
C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
- Additional Instructions to Support Complex Multiplies
C64x+ L1/L2 Memory Architecture
- 32K-Byte L1P Program RAM/Cache (Direct Mapped)
- 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
- 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
ARM926EJ-S Core
- Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
- DSP Instruction Extensions and Single Cycle MAC
- ARM® Jazelle® Technology
- EmbeddedICE-RT™ Logic for Real-Time Debug
ARM9 Memory Architecture
- 16K-Byte Instruction Cache
- 8K-Byte Data Cache
- 16K-Byte RAM
- 8K-Byte ROM
Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
Endianness: Little Endian for ARM and DSP
Video Processing Subsystem
- Front End Provides:
  - CCD and CMOS Imager Interface
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
  - Glueless Interface to Common Video Decoders
  - Preview Engine for Real-Time Image Processing
  - Auto-Exposure, Auto-White Balance and Auto-Focus Module
  - Histogram Module
  - Resize Engine
    - Resize Images From 1/4x to 4x
    - Separate Horizontal/Vertical Control
- Back End Provides:
  - Hardware On-Screen Display (OSD)
  - Four 54-MHz DACs for a Combination of
    - Composite NTSC/PAL Video
    - Luma/Chroma Separate Video (S-video)
    - Component (YPbPr or RGB) Video (Progressive)
  - Digital Output
    - 8-/16-bit YUV or up to 24-Bit RGB
    - Up to 2 Video Windows
    - HD Resolution
External Memory Interfaces (EMIFs)
- 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
- Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach
  - Flash Memory Interfaces
    - NOR (8-/16-Bit-Wide Data)
    - NAND (8-/16-Bit-Wide Data)
Flash Card Interfaces
- Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
- SmartMedia
- CompactFlash Controller With True IDE Mode
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit Watch Dog Timer
Three UARTs (One with RTS and CTS Flow Control)
Master/Slave Inter-Integrated Circuit (I²C Bus™)
One Serial Port Interface (SPI) With Two Chip-Selects
Audio Serial Port (ASP)
- I2S
- AC97 Audio Codec Interface
- Standard Voice Codec Interface (AIC12)
10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Media Independent Interface (MII)
VLYNQ™ Interface (FPGA Interface)
Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
USB Port With Integrated 2.0 PHY
- USB 2.0 High-/Full-Speed (480-Mbps) Client
- USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
Three Pulse Width Modulator (PWM) Outputs
Individual Power-Saving Modes for ARM/DSP
Flexible PLL Clock Generators
ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
361-Pin Pb-Free BGA Package (ZWT Suffix), 0.8-mm Ball Pitch
3.3-V and 1.8-V I/O, 1.2-V Internal
0.09-µm/6-Level Cu Metal Process (CMOS)

More info: TI’s DM6446 Davinci Digital Media SoC

RSS 2.0 feed.

Possible Related Entries: