DesignWare Serial ATA (SATA) Advanced Host Controller Interface (AHCI) - Synopsys

Synopsys add new library to its DesignWare solution. The company announced the release its DesignWare Serial ATA (SATA) Advanced Host Controller Interface (AHCI) solution. With this library, Synopsys offers all the required elements of a SATA AHCI interface including the SATA AHCI Digital Host Controller, SATA Verification IP (VIP) and SATA PHY.

The Synopsys DesignWare IP solutions for SATA include a comprehensive set of synthesizable IP, verification IP, PHYs and an automated method for subsystem assembly when the Synopsys coreAssembler tool is used. The configurable architecture of the IP, coupled with the automated assembly tool, dramatically reduces the complexity of designing next-generation SATA-based subsystems and significantly improves overall productivity for a faster time to results. The SATA digital cores are compliant with the SATA 2.6 specification, the SATA AHCI core is compliant with the AHCI 1.1 specification and both cores include an ARM AMBA 2.0 compliant subsystem interface.

DesignWare Serial ATA Solutions

Describing the register-level interface for a host controller, The AHCI specification provides a standardized hardware and software interface to reduce integration cost. This SATA solution provides an easy-to-integrate solution that enables designers developing SATA AHCI-compliant systems to quickly implement a full-featured SATA host interface with native AHCI in their designs.

Key features of DesignWare Serial ATA Solutions:

• Digital Core IP
  • Reduce cost of deployment with silicon proven core
  • Verilog testbench simplifies writing customized tests and enables post integration testing
  • Easy to integrate with configurable PHY interface to support multiple PHY vendors
• Verification IP
  • Broadest verification IP portfolio in the industry
  • Supports proven verification methodology for SystemVerilog
  • Delivers 5X simulation performance improvement with VCS
  • Includes example testbenches to accelerate learning and speed testbench development

The DesignWare SATA AHCI core is compliant with the SATA 2.6 specification and AHCI 1.1 specification, and includes an ARM AMBA 2-compliant subsystem interface. With the industry-standard software and hardware interfaces, designers can reduce the time required to integrate the core into their design. The DesignWare SATA AHCI core has been verified against the industry-standard AHCI software drivers provided as part of the Linux and Windows Vista operating systems. The AHCI standard programming interface reduces custom platform software driver creation, which in turn reduces the overall time from prototype to production. To meet the needs of low-power device operation, the DesignWare core includes aggressive power management strategies that enable the core to both initiate power-down modes and allow clocks to be turned off in these modes, resulting in very-low power consumption. The integrated Direct Memory Access (DMA) and configurable multiple independent SATA ports help ensure high performance operation on both the SATA interface and the system bus interface.

The core is delivered with DesignWare Verification IP and includes a subset of directed and constrained random tests to verify that the user-defined configuration functions correctly. The designer can leverage these tests and Verification IP to jumpstart the subsystem and system-level application-specific verification. The DesignWare SATA AHCI controller and the DesignWare SATA PHY constitute a seamlessly integrated, pre-verified SATA AHCI-compliant solution that accelerates time-to-market and reduces risk. In addition, the DesignWare SATA AHCI controller includes a highly configurable PHY link layer which has been proven to be interoperable with many third-party SATA PHYs.

Further reading: DesignWare Serial ATA (SATA) Advanced Host Controller Interface (AHCI)