Cypress West Bridge Antioch and Synopsys Galaxy™ RTL-to-GDSII

Synopsys, Inc. announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to-GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation

Built on Synopsys’ gold-standard Star-RCXT™ extraction and PrimeTime® sign-off technologies, PrimeRail offers full-chip analysis, dynamic memory and macro-modeling capabilities for advanced multi-voltage, low-power, high-performance designs. Its multimode analysis capability enables users to pinpoint and mitigate problems with critical power-up rush current or excessive current during wake-up to active mode in MTCMOS designs. PrimeRail is integrated with the Galaxy design platform, allowing designers to predict voltage drop during floorplanning, perform pre- and post-layout analysis with on-chip decoupling capacitance, and achieve full-chip sign-off with package parasitics.

Source: Synopsys