CEVA-X1641 DSP for VoIP Phone System, WiMAX, 3G, 4G

CEVA, Inc has announced (Oct 30,2006) Quad-MAC DSP core, the CEVA-X1641, newest addition to the company’s industry-proven family of CEVA-X DSP cores. CEVA-X1641 is designed to run highly computational intensive tasks that require substantial data throughput and high memory.

CEVA-X1641 provides customers with the flexibility to configure the optimal memory size and structure for their specific application such as WiMAX, WiBro, 3G LTE ( Long Term Evolution ),  H.264 compression standard and VC1. The CEVA-X1641 provides a high-performance, low-power platform allowing its licensees to develop multi-mode products (e.g., 2G/3G/4G processors) and to reuse the same platform for next-generation standards such as 802.16e, WiBro, Flash-OFDM, UMTS and TD-SCDMA.

CEVA’s DSP core is a combined VLIW/SIMD architecture, designed to handle high-performance and data-throughput requirements of 4G technologies and multimedia applications. Highly computational intensive technologies such as WiMAX are calling for the use of 4 MAC units, coupled with a 128bit data memory bandwidth, to handle the extremely high data rates capable of reaching 100Mbps.

VLIW (Very Long Instruction Word) architectures allows a high level of concurrent instructions processing thus providing extended parallelism and efficient power consumption.

SIMD (Single Instruction Multiple Data) architectures allows single instructions to operate on multiple data elements resulting in code size reduction and increased performance.

CEVA-X1641 also incorporates specialized video instructions and mechanisms to accelerate multimedia processing in applications like mobile TV and video conferencing.

Gideon Wertheizer, CEO of CEVA said:

…The CEVA-X1641 DSP core is in line with our strategy to offer platforms that will support the growing need for performance and power-efficient DSPs for emerging wireless and multimedia standards,…

…Our new, high-performance and fully synthesizable CEVA-X1641 DSP core will enable customers to expedite their time-to-market and reduce development costs by using the same platform across multiple, differentiated products…

Compatibility:

CEVA-X1641 is compatible with CEVA-X1620™ and CEVA-X1622™ DSP cores, enabling licensees of the CEVA-X1641 to leverage the broad range of software and components already available for the CEVA-X architecture.

CEVA-X1641 architecture is implemented in a small size, only 5 percent larger than its predecessor (CEVA-X1620)
 

Picture: CEVA-X1641 Block Diagram

CEVA-X1641 architecture is compiler-driven, implementing orthogonal instruction set and operands, load/store architecture, byte addressing and simple memory configuration (no X/Y partitioning).

The Computation and Bit Manipulation Unit is responsible for all DSP computations, and includes four independent functional units: Four 16×16-bit MAC units, 40-bit Shift unit and 40-bit Logical unit.

The Data Address and Arithmetic Unit includes two identical Load/Store Units, responsible for generating all data memory accesses. The Scalar Unit is a 32-bit integer CPU block, supporting arithmetic, shift and bit manipulation operations on 32-bit data types.

The Program Control Unit is responsible for the code flow, including sequential flow, branches, loops and interrupts. The Dispatch Unit analyses instruction packets and dispatches single instructions to the different functional units.

The data memory subsystem supports a user configurable size L1 memory and up to 4G byte of L2 memory, through an AHB-Lite system bus and a programmable DMA. The program memory subsystem supports a user configurable size of L1 memory, with or without a 32KB program cache. Using a separate AHB-Lite system bus and a programmable DMA, these can be extended up to 4G byte in L2.

A separate IO space is used for peripherals and slow devices built around the DSP.

The CEVA-X1620 achieved the highest score for a licensable dual MAC DSP from BDTI (as measured by BDTIsimMark2000™), and the CEVA-X1641 is reaching even higher performance levels. To accomplish that, dedicated instructions and mechanisms were built into the architecture, supporting 1-cycle Viterbi butterfly (two ACS), 1.2-cycles FFT butterfly and various functions accelerating multimedia kernels.

CEVA-X1641 design implementations are Soft Core based, allowing the customer to select the optimal operating point in terms of die size, power consumption and performance. In addition, the customer has complete flexibility in selecting the foundry, process (e.g. 0.13µ, 90nm, 65nm) and complementary IPs.

CEVA-X1641 IP incorporates fully automated design flow supporting mainstream EDA tools, significantly shortens time-to-market. CEVA-X1641 design can be ported to an FPGA that can be used for product prototype, system integration, design acceleration and clarification.

CEVA, Inc., suggest their CEVA-X1641 for these markets/applications:

• 4G and WiMAX cellular handsets, smartphones and PDAs
• Multimedia processing (video ana audio) for mobile devices
• VoIP Gateways and broadband modems
• Home entertainment (Digital TV, HDTV, PVR, HD-DVD)

Specification and Key features:

• Quad MAC 16-bit fixed point DSP
• Combination of VLIW and SIMD architecture concepts
• Up to 8 instructions issued simultaneously
• Variable instruction width (16/32-bit) and variable length of instruction packets
• Two level memory architecture
• Up to 4G byte addressable memory space
• 64K/96K/160K byte L1 program memory and cache
• 64K/128K byte L1 data memory
• Program and data DMAs
• Nine stage pipeline
• All instructions can be conditionally executed

CEVA, Inc other DSP Cores:

• CEVA-X1641
• CEVA-X1622
• CEVA-X1620
• CEVA-Teak
• CEVA-TeakLite-II
• CEVA-TeakLite

Source: CEVA