CEVA-X1620 DSP core and CEVA-XS1200 Subsystem for RadioFrame’s Femtocell Base Stations

CEVA announced that RadioFrame has licensed the CEVA-X1620 DSP core and CEVA-XS1200 subsystem for the development of next-gen femtocell base stations. RadioFrame will utilize CEVA-X DSP and subsystem to handle the compute-intensive baseband processing for their base stations. Femtocell base stations are deployed to increase and improve cellular coverage and capacity indoors and to enable fixed mobile convergence in the home.

One of Radioframe’s Femtocell Base Stations

Cell phones are normally reliable on the go, but in areas such as the home
or office, or even remote areas where cell signals are often too weak, it can be
difficult or impossible to have extended conversations with a reliable cell
signal.  Radioframe’s femtocell base stations were designed for the home environment, where a adequate cell phone signal is often unavailable. Femtocell base station is also an option for lower cost alternative to traditional land-line communication services. RadioFrame Femtocell base station  offer
a replacement to the traditional land line telephone service, giving a strong cell signal where cellular subscribers spend most of their time. Consumers will recognize femtocell base station as a simple mini module in their home, which connects to internet modem, providing them with strong signal.

CEVA-X1620 Dual MAC DSP Core

The CEVA-X1620 is a dual MAC 16-bit, fixed point, fully synthesizable DSP core, running up to eight instructions simultaneously. It provides variable instruction widths, two-level memory architecture and up to 4G bytes of addressable memory space. It has been licensed and adopted by major semiconductor manufacturers in the 3G baseband and mobile multimedia markets.

CEVA-X1620 DSP Core implement CEVA-X DSP family
consisting of 16-bit data width and two MAC units. CEVA-X1620 target
markets include 3G cellular handsets and Software radio, smart phones
/ PDAs, Video & Audio processing for mobile devices, VoIP Gateways
& broadband modems, and home entertainment (Digital TV, HDTV, PVR,
HD-DVD).

CEVA-X1620 Dual MAC DSP Core Block Diagram

Key features of  CEVA-X1620 DSP Core:

• Dual MAC 16-bit fixed point DSP
• Combination of VLIW and SIMD architecture concepts
• Variable instruction width (16/32-bit) and variable length of instruction packets
• Up to 8 instructions issued simultaneously
• Two level memory architecture
• Up to 4G byte addressable memory space
• 64K byte L1 data memory
• 64K byte L1 program memory and cache
• Program and data DMAs
• All instructions can be conditionally executed
• Nine stage pipeline

High Performance at Low Power Consumption
The CEVA-X1620 Dual MAC DSP Core architecture has a unique mix of Very Long Instruction Word and Single Instruction Multiple Data  architectures.
The Very Long Instruction Word  architecture allows a high level of concurrent instructions
processing thus providing extended parallelism, as well as low power
consumption.

Single Instruction Multiple Data architecture allows single instructions to operate on multiple
data elements resulting in code size reduction and increased performance.
Low power consumption is also achieved in the CEVA-X1620 by its
instructions and dedicated mechanisms such as dynamic and selective
units shutdowns and clock slow downs.

High-level
Programming
CEVA-X1620 Dual MAC DSP Core architecture is compiler-driven, implementing orthogonal instruction set and operands, load/store architecture, byte addressing and simple memory configuration (no X/Y partitioning) The Computation and Bit Manipulation Unit is responsible for all
DSP computations, and includes four independent functional units:
Two 16×16-bit MAC units, 40-bit Shift unit and 40-bit Logical unit.

The Data Address and Arithmetic Unit includes two identical Load/Store
Units, responsible for generating all data memory accesses. The
Scalar Unit is a 32-bit integer CPU block, supporting arithmetic,
shift and bit manipulation operations on 32-bit data types.

The Program Control Unit is responsible for the code flow, including
sequential flow, branches, loops and interrupts. The Dispatch Unit
analyses instruction packets and dispatches single instructions
to the different functional units.

The data memory subsystem supports 64K byte of L1 memory and up to 4G
byte of L2 memory, through an AHB-Lite system bus and a programmable DMA.
The program memory subsystem supports 64K byte of L1 memory, or 32K byte
L1 memory and 32K byte cache. Using a separate AHB-Lite system bus and
a programmable DMA, these can be extended up to 4G byte in L2.

Soft
Core
CEVA-X1620 Dual MAC DSP Core design implementations are Soft Core based, allowing the customer
to select the optimal operating point in terms of die size, power consumption
and performance. In addition, the customer has complete flexibility in
selecting the foundry, process (e.g. 0.13µ, 90nm, 65nm) and complementary IPs.

CEVA-X1620 IP incorporates fully automated design flow supporting mainstream
EDA tools, significantly shortens time-to-market. CEVA-X1620 DSP Core design can
be ported to an FPGA that can be used for product prototype, system integration,
design acceleration and clarification.

CEVA-XS1200 DSP System Platform

The CEVA-XS1200 DSP system platform is a highly integrated SoC platform, designed to ease the development and integration process and further reduce development costs and time to market for CEVA-X-based designs. CEVA-XS1200 utilizes multiple innovative power-saving techniques such as activating the system modules only when needed; level-two memory architecture and caching; adjustable DSP system speed; decentralized interconnect topology; and selective hardware/software wake-up events.

CEVA-XS1200 DSP System Flatform Block Diagram

CEVA-XS1200 contains a 3D DMA co-processor and glue-less TDM ports, providing designers with the ability to target high-performance applications such as multimedia, communications, VoIP, storage and more. The platform includes a complete set of DSP peripherals and interfaces, including an interrupt controller, power management unit, timers and general purpose I/Os, and it also provides easy means of connectivity to other systems present on chip.

Key features of CEVA-XS1200 DSP system platform:

• High Performance VLIW SIMD Architecture with Nine stages pipeline
• Tightly coupled Architecture extensions to connect external Hardware
• Concurrent execution of up to 8 instructions in parallel
• Compiler driven load store orthogonal Architecture
• Special instructions for specific applications accelerations
• Variable instruction width (16 or 32-bit) and variable length of instruction packets
• Two Levels Memory with Up-to 4G-bytes address space
• Internal DMA and Cache Memory Subsystem

With the addition of off-the-shelf software provided by CEVA and
its CEVAnet 3rd Party technology partners, the CEVA-XS Platform
suits a wide range of applications such as Communications, Multimedia,
VoIP, Storage and more.

The CEVA-XS1200 is a multimedia system platform incorporating many peripherals,
including specialized ones for Video/Audio processing such as a programmable
3-D DMA co-processor and glue-less interface TDM and SPI ports.

About CEVA, Inc.
CEVA is the licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry. CEVA licenses a family of programmable DSP cores, associated SoC system platforms and a portfolio of application platforms including multimedia, audio, Voice over Packet (VoP), Serial Attached SCSI (SAS) and Serial ATA (SATA)

About RadioFrame Networks, Inc.
RadioFrame Networks, Inc. is modular radio solutions for telecom operators. The company deploys cost-effective radio access via flexible and efficient software driven base stations. RadioFrame Networks offers an agile, multiple-technology, future-proof solution that integrates into existing networks, increases capacity, and reduces operating costs and capital expenditures. The company is going to use CEVA-X1620 DSP core and CEVA-XS1200 Subsystem for its RadioFrame Femtocell Base Stations.