C to RTL for FPGA and ASIC Designs - CebaTech

CebaTech’s C-to-RTL (C2R) Compiler enables full-chip designs to be architected, verified, and implemented using ANSI C as the design language, instead of using the traditional RTL-based design approach. CebaTech claim that this new approach can speed up programming process two to three times.

C2R generates synthesizable Verilog RTL from untimed ANSI C. Hardware architecture is defined in the C code. Software engineers working with hardware architects can rapidly create accelerated hardware implementations of software algorithms.

Chad Spackman, CebaTech, said:

The C2R Compiler was invented to consume an enormous, robust, open-source C code base…

…It was our desire to capture the integrity of that software in hardware and to impose an architecture that would allow the integrity of the design to be verified in a standard C development environment…

…Our compiler has enabled us to create a hardware implementation of the complete TCP/IP stack for 10G applications…

CebaTech's C-based ESL design methodology and C2R Compiler allow fast changes to the system architecture, enabling extensive exploration of design tradeoffs to achieve the optimal design. The functional verification of the hardware design is performed in native C. This eliminate the dependence on RTL simulation.

CebaTech’s C2R Compiler is available for FPGA and ASIC designs. The price starts at US$145,000.

Source: CebaTech