ASSET Offers Test Lab for Validating JTAG Design

ASSET InterTech, Inc., has opened the Design-for-Test (DFT) Lab for validating the JTAG infrastructure in chip and printed circuit board designs. ASSET InterTech is a company specialized on boundary-scan (JTAG/IEEE 1149.1) test.

Arden Bjerkeli, ASSET's director of support, said:

Today there are several test and programming methodologies which depend upon an effective boundary-scan infrastructure. Without a properly designed JTAG infrastructure, these advanced methodologies can’t perform their functions

The lab will offer a free analysis of pre-prototype designs and advice to ensure that the JTAG infrastructure can be effectively deployed in its traditional structural test applications as well as in advanced applications that take advantage of the JTAG infrastructure.

The services of the lab are available to first-time users of boundary scan. Scott Creekpaum has been named manager of the lab.

The free analysis and design recommendations will be performed with ASSET's DFT Analyzer, tool that automatically verifies the JTAG testability of board designs. The accuracy of a chip design's Boundary-scan Description Language (BSDL) file will be verified with the BSDL Validation Service.

More info on ASSET InterTech