Arria GX FPGAs offer Support up to 3.125 Gbps Transceiver and Additional Serial Protocols - Altera

Altera’s Arria GX FPGA family (based on Stratix II GX) now support for
transceiver speeds up to 3.125 Gbps. Arria GX FPGAs also provide support for
more protocols, including XAUI, SDI, CPRI, OBSAI and SerialLite II, along with
the ability to develop proprietary, serial-based IP using its Basic mode…

Key features of Arria GX FPGAs include:

• Transceiver block features
  • High-speed serial transceiver channels with clock/data recovery support
    up to 3.125 Gbps.
  • Devices available with 4, 8, or 12 high-speed full-duplex serial
    transceiver channels
  • Support for the following CDR-based bus standards - PCI Express, Gigabit
    Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the
    ability to develop proprietary, serial-based IP using its Basic mode
  • Individual transmitter and receiver channel power-down capability for
    reduced power consumption during non-operation
  • 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter
    output buffers
  • Receiver indicator for loss of signal (available only in PCI Express
    (PIPE) mode)
  • Hot socketing feature for hot plug-in or hot swap and power sequencing
    support without the use of external devices
  • Dedicated circuitry that is compliant with PIPE, XAUI, GIGE, SDI, and
    Serial RapidIO
  • 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to
    8-bit decoding
  • Phase compensation FIFO buffer performs clock domain translation between
    the transceiver block and the logic array
  • Channel aligner compliant with XAUI
• Main device features:
  • TriMatrixTM memory consisting of three RAM block sizes to implement true
    dual-port memory and first-in first-out (FIFO) buffers with performance up
    to 380 MHz
  • Up to 16 global clock networks with up to 32 regional clock networks per
    device
  • High-speed DSP blocks provide dedicated implementation of multipliers,
    multiply-accumulate functions, and finite impulse response (FIR) filters
  • Up to four enhanced PLLs per device provide spread spectrum,
    programmable bandwidth, clock switch-over, and advanced multiplication and
    phase shifting
  • Support for numerous single-ended and differential I/O standards
  • High-speed source-synchronous differential I/O support on up to 47
    channels
  • Support for source-synchronous bus standards, including SPI-4 Phase 2
    (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
  • Support for high-speed external memory including double data rate (DDR
    and DDR2) SDRAM, and single data rate (SDR) SDRAM
  • Support for multiple intellectual property megafunctions from Altera®
    MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)
  • Support for remote configuration updates

Press Release:

Altera Broadens Markets for Arria GX Family

Increases Transceiver Performance, Expands Protocol Support and Reduces
Power

Altera Corporation (NASDAQ:ALTR) announced its Arria GX FPGA family now
offers support for transceiver speeds up to 3.125 Gbps, additional serial
protocols and reduced static power. Based on the proven Stratix II GX
technology, Arria GX FPGAs are designed to deliver robust signal integrity at a
low price for higher volume applications. The increased transceiver speeds,
expanded protocol support and reduced static power enables the Arria GX family
to deliver greater value in communications, broadcast, computer, storage and
industrial markets.

The Arria GX family includes increased performance and function of the
transceivers to drive serial interfaces at speeds from 600 Mbps up to 3.125 Gbps
and a reduction in static power of up to 20 percent. In addition, Arria GX FPGAs
provide support for more protocols, including XAUI, SDI, CPRI, OBSAI and
SerialLite II, along with the ability to develop proprietary, serial-based IP
using its Basic mode. The Arria GX family continues to support PCI Express (PCIe),
Gigabit Ethernet (GbE) and Serial RapidIO (SRIO) protocols. The upgraded device
also includes performance-enhancing features such as channel equalization. Arria
GX FPGAs utilize flip-chip packaging technology that provides superior signal
integrity compared to wire-bond packages.

"We’ve expanded our initial Arria GX product offering to address an
increasing number of applications requiring additional transceiver performance,"
said Luanne Schirrmeister, director of marketing, low-cost products at Altera
Corporation. "We’ve enhanced an award-winning FPGA family by expanding the
serial protocol support to focus on higher volume applications."

The Arria GX family is comprised of five devices ranging in density from 21K
to 90K LEs, up to 4.5 Mbits of embedded memory and up to 176 multipliers. The
family is built on Taiwan Semiconductor Manufacturing Company’s (TSMC’s)
established 90-nm process.

Comprehensive Software and IP Support
Arria GX FPGAs utilize the industry-leading Quartus II design software to
accelerate compile times, helping users expedite time to market. With
outstanding software tools, verified intellectual property (IP) cores, complete
characterization reports, reference designs, and excellent support, customers
can begin designing immediately with Arria GX devices.

An advanced version of the Arria GX datasheet can be downloaded at http://www.altera.com/literature/hb/agx/agx_5v1_01_advanced_copy.pdf.
Quartus II software version 7.2 is available at www.altera.com/download. An
upgraded version of Quartus II software will be available soon; designers can
complete their Arria GX design using Quartus II v7.2 software, and then port the
design to new software version.

Pricing and Availability
Pricing for the upgraded Arria GX devices will remain the same as the initial
version, US$50 for the EP1AGX50CF484C6 device in 25K unit volume. All Arria GX
devices are shipping and available. The Arria GX Development Kit is available
for ordering through the Altera online store at http://www.altera.com/products/devkits/altera/kit-arriagx.html

About Altera
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