ARM Cortex-M0 Ultra Low Power Processor

Earlier this year, ARM introduced the Cortex-M0, a new ultra low power, low gate count, 32-bit ARM processor. The new Cortex-M0 is able to deliver 0.9 DMIPS/MHz (dhrystone) and comparable performance to the synthesizable version of the ARM7TDMI. It consumes as little as 0.085 milliwatts/MHz in an area of under 12K gates. ARM Cortex-M3 processor ideal for ultra low power microcontroller and mixed signal applications including power control, motor control, medical devices, gaming accessories, e-metering, ZigBee (IEEE 802.15.4) and Z-Wave systems. The Cortex-M0 processor is also suitable for programmable mixed signal applications such as intelligent sensors and actuators (traditional solution require separate digital and analog devices).

ARM Cortex-M0 Processor

The ARM Cortex-M0 processor maintain tool and binary compatibility with the ARM Cortex-M3 processor. The Corex M0 maintains the nested vector interrupt controller (NVIC) and the wake-up interrupt controller (WIC) from the Cortex M3 design, which is one of the keys to allowing the Cortex-Coetex M0 to start up quickly, execute and then fall back to energy-conserving sleep mode. The result is the Cortex M0 occupies about one-third the area and consumes about half the dynamic power of the Corex M3. Both the Cortex-M0 and Cortex-M3 make use of the ARM AMBA bus as the means to link peripherals to the core. ARM has taken the direct memory access (DMA) controller out of the processor core and implemented a mini DMA memory controller as AMBA-bus peripheral.

Benefits of ARM Cortex-M0 processor:

• 32-bit performance in a 16-bit footprint
• Power efficiency
• Lower cost (smaller processing core, system and memories)
• Processor and analog circuits can be implemented in single chip
• Thumb (16-bit) instruction set for maximum code density
• Fast interrupt handling
• Wake-up Interrupt Controller enables instantaneous active mode for critical events
• C language programming (no assembler code required)
• Enhanced system debug
• Wide application, including ultra low cost microcontrollers and analog mixed signal applications

The low-power operation of the Cortex-M0 processor is enhanced by the ARM Ultra High Density Standard Cell Library for the 180ULL (Ultra Low Leakage) process, the ARM Power Management Kit (PMK), low power memory instances built specially for Cortex-M0, and the Keil Microcontroller Development Kit (MDK). The ARM low power libraries are optimized to enable low dynamic and static power consumption and minimize chip area. The PMK features dynamic and leakage power management functions and the low power memory instances support external power gating for extreme leakage reduction.

ARM Cortex-M0 processor is fully supported by the Keil ARM MDK, which integrates the ARM RealView Compilation Tools with the new Keil µVision4 IDE and Debugger. The Keil µVision4 IDE has been designed to enhance developer’s productivity, enabling faster, more efficient program development. The Keil µVision4 introduces a flexible window management system, enabling developers to drag and drop individual windows anywhere on the visual surface including support for multiple monitors.

ARM Cortex-M0 processor-based designs can also be prototyped using the ARM Microprocessor Prototyping System (MPS), which features:

• A Cortex-M0 or Cortex-M3 processor operating at up to 50MHz in FPGA
• Altera Stratix III (EP3SL50) FPGA for system prototyping
• RS232, USB, Ethernet, CAN, FlexRay, Audio, DVI, MMC
• Free synthesis and Place and Route Tool

ARM Cortex-M0 processor is also supported by third-party tool and RTOS vendors including IAR Systems, CodeSourcery, Mentor Graphics, Code Red, SEGGER, Express Logic and Micrium.

ARM Cortex-M0 processor is compatible with the Cortex Microcontroller Software Interface Standard (CMSIS), the vendor-independent hardware abstraction layer for the Cortex-M processors. CMSIS enables consistent and simple software interfaces to the processor, simplifying software re-use, reducing the learning curve and time-to-market.

NXP LPC1100 Cortex-M0 based Microcontroller

On March 22, NXP introduced the LPC1100, the first functional ARM Cortex-M0 based Microcontroller series, which is scheduled to be on market at the beginning of 2010. LPC1100 will target broad applications such as battery applications, consumer peripherals, e-metering and remote sensors.

NXP LPC1100 ARM Cortex-M0 based Microcontroller

Key features of NXP LPC1100 Cortex-M0 based Microcontroller:

• ARM Cortex-M0 processor
  • 50-MHz operation
  • Nested Vectored Interrupt Controller for fast deterministic interrupts
  • Wakeup Interrupt Controller allows automatic wake from an priority interrupt
  • Three reduced-power modes: Sleep, Deep-sleep, and Deep power-down
• Memories
  • Up to 128 KB Flash memory
  • Up to 16 KB SRAM
• Analog Peripherals :
  • 10-bit Analog-to-Digital Converter with eight channels and conversion rates up to 250K samples per second
• Serial Peripherals
  • UART with fractional baud rate generation, internal FIFO, and RS-485 support
  • SPI controller with FIFO and multi-protocol capabilities
  • I2C-bus interface supporting full I2C-bus specifi cation and Fast mode plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode
• Other peripherals :
  • Up to 42 General Purpose I/O (GPIO) pins with confi gurable pull-up/down resistors and a new, confi gurable open-drain operating mode
  • Four general purpose counter/timers, with a total of four capture inputs and 13 match outputs
  • Programmable Watchdog Timer (WDT) with lock-out feature
  • System tick timer
  • Each peripheral has its own clock divider for power savings

NXP LPC1100 ARM Cortex-M0 based Microcontroller - Block Diagram

Additional features

• Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, and Deep powerdown modes
• Clock generation unit with divider that can reflect the main oscillator clock, IRC clock, CPU clock, and Watchdog clock.
• Processor wake-up from Deep-sleep mode via interrupts from various peripherals
• Serial Wire Debug and Serial Wire Trace Port
• 15 GPIO pins can be used as edge and level sensitive interrupt sources
• Crystal oscillator with an operating range of 1 MHz to 25 MHz
• 12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock
• PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the Watchdog oscillator.
• Brownout detect with four separate thresholds for interrupt and forced reset
• Power-On Reset (POR)
• High-current output driver (20 mA) on one pin
• High-current sink drivers (20 mA) on two pins
• Single 3.3 V power supply (1.8 V to 3.6 V)
• Available as 48-pin LQFP package and 33-pin HVQFN package

References:

• Press release: ARM Launches its Smallest, Lowest Power, Most Energy Efficient Processor (_http://www.arm.com/news/24418.html)
• Press release: NXP Demonstrates World’s First Functional Cortex-M0 Silicon (_http://www.standardics.nxp.com/news/first.arm.cortex-m0.silicon/)
• ARM preps tiny core for low-power microcontrollers (_http://www.eetimes.com/cleanterra/article/printableArticle.jhtml?articleID=214502333&printable=true)
• NXP 50-MHz, 32-bit Cortex-M0 microcontrollers LPC1100 (_http://www.standardics.nxp.com/literature/leaflets/microcontrollers/pdf/cortex-m0.lpc11xx.pdf)
• ARM Cortex-M0 (_http://www.arm.com/products/CPUs/ARM-Cortex-M0.html)