Altera Quartus II v7.1 Featuring Faster Compile Times and Smaller Memory Footprint

Altera released the Quartus II software version 7.1, featuring faster compile time and smaller memory footprint.  Quartus II version 7.1 can be used for all members of Altera's recently announced product families, including, Arria GX and Stratix III.

Chris Balough, Altera, stated:

Altera have a commitment to its customers to deliver cutting-edge performance and productivity…

As the only FPGA vendor to offer 64-bit Windows and multi-processor support, in addition to faster compile times and reduced memory usage, Altera provides significant advantages when compared with competitors…

Using advanced place-and-route algorithms, Quartus II software version 7.1 and Stratix III FPGAs deliver, on average, more than 2X faster compile times when compared to competing high-end 65-nm FPGAs. To further accelerate the design cycle, customers using multi-processor computers see an additional 20 percent reduction in compile times over single-processor computers. Altera's Quartus II software is the only software from an FPGA vendor offering multi-processor (e.g., the Intel Core 2 Duo and Quad and AMD Athlon 64 X2) support, taking advantage of today's dual- and quad-core computers.

This Quartus II software version 7.1 also includes several productivity updates to Altera's SOPC Builder automated system development tool. An improved infrastructure and a more responsive GUI allows for faster implementation of large systems, and a new Avalon Streaming interface is optimized to send streaming data between two intellectual property (IP) blocks. Quartus II software version 7.1 also includes a new Avalon Memory-Mapped clock-crossing bridge, a pipeline bridge and a scatter-gather direct memory access (DMA) controller for improved system performance.

Version 7.1 of Quartus II software includes a number of features and enhancements to help customers achieve the highest productivity and performance when designing with Altera FPGAs, CPLDs and structured ASICs.

• Faster TimeQuest timing analyzer - Improves productivity with faster timing closure featuring improved compile time, less memory usage and easier conversion from Altera's classic timing analyzer.
• New in-system sources and probes editor - Reduces verification time by allowing designers to drive stimuli to the device and sample internal nodes during run time.
• New compile-time advisor - Recommends compile-time saving settings during the design flow to improve productivity.
• Expanded synthesis - Provides faster design entry with a new text editor, new HDL templates and true dual-port RAM inferencing.
• Enhanced usability - Simplifies the design process and accelerates the sign-off process by using the advanced Quartus II message console.
• Updated parallel flash loader - Offers quicker device configuration with 2X faster flash programming times and burst mode support for flash devices.
• Smart notification - Automatic notifications via the Quartus II desktop of new software downloads and service packs.

Both Free Web Edition and Subscription Edition of Quartus II software version 7.1 are available for download. The Subscription Edition is also available in DVD format by request at Altera’s website. Subscribers receive Quartus II software, the ModelSim -Altera edition and a full license to the IP Base Suite, which includes ten of Altera's most popular IP (DSP and memory) cores.

The annual software subscription is $2,000 for a node-locked PC license. Quartus II design software supports major operating systems, including Microsoft Windows XP Professional x64, Microsoft Windows XP and 2000, UNIX (Solaris 8 and 9), Red Hat Enterprise Linux 3.0 and 4.0, and SUSE Enterprise Linux 9.

Further reading: Altera Quartus II Software version 7.1