Altera Cyclone III FPGA Overview

Altera announced the immediate availability of the Cyclone III FPGA family. The new chips are build using 65 nm technology, delivering up to 120K LEs (Logic Elements), up to 4 Mbits memory and up to 288 DSP multipliers. Altera claim, Cyclone III offers 20% lower cost per LE than the previous company’s products, and consume 75% less power than competing FPGAs.

Altera Cyclone III FPGA Chip

Key Features of the Cyclone III FPGAs

Optimized for Low Power Applications

Cyclone III FPGAs are optimized for low power applications, help developers to manage thermal requirements, reduce system cooling costs, and extend battery life for handheld applications. At a 20 MHz operating frequency, largest Cyclone III device, the 120K LE EP3C120, consumes less than 600 mW. At 100 MHz the EP3C120 consumes less than 2 Watts.

High density low-cost FPGA

With up to 120,000 logic elements (LEs), 4 Mbits of on-chip memory, and 288 embedded 18 x 18 multipliers, the Cyclone III device family offers very high density low-cost FPGA family. The rich supply of logic, memory and multipliers and low power consumption enable manufacturers to use Cyclone III FPGAs in the heart of cost-sensitive application such as H.264 encoder, digital television (DTV), pico BTS  and software defined radio (SDR). Following table show devices overview of Cyclone III.

Rich DSP supports

Developers can use Cyclone III FPGAs alone or as DSP coprocessors for DSP applications such as wireless communications systems, video and image processing,  and other common DSP functions.

The embedded multipliers in Cyclone III FPGAs are capable of implementing the simple multiplication operation commonly used in typical DSP functions. Multipliers can be inferred directly from VHDL or Verilog source code. Cyclone III devices offer up to 288 embedded multiplier blocks. Multipliers can be cascaded to support wider bit widths.

The Quartus II software includes functions that control the mode of operation of the embedded multiplier blocks based on user parameter settings.

The DSP support resources offered by Cyclone III FPGAs are shown in following table:

Cyclone III devices have been optimized for low-cost DSP applications as shown in following table:

Larger Embedded Memory

The on-chip memory of Cyclone III FPGAs is 3.5 times compared to previous low-cost FPGA generations. With up to 4 Mbits of embedded memory, designer will be able to design cost effective next generation products.

The embedded memory structure of Cyclone III FPGAs consists of 9,216-bit blocks. The M9K memory blocks allow optimal usage for memory intensive applications and DSP intensive applications. Each M9K block can be used in different widths and configurations including FIFO, packed mode and true dual-port mode. In addition, the clock read and write enables increase the flexibility of use and allows for reduced power consumption.

Clock Management

Large FPGA applications need good clock management. Cyclone III FPGAs include global clocking structure and PLLs. The larger devices have up to 20 global clocks which can also be used as global signals. When not in use, the clock system can also be powered down to save power.

Cyclone III FPGAs have up to 4 enhanced PLLs that provide advanced clock management capabilities such as dynamic reconfiguration, cascadability, programmable phase shift, external clock output, programmable duty cycle, lock detection, spread spectrum input clocking, and high-speed differential support on the input and output clocks.

Connectivity of  the Cyclone III FPGAs

External Memory Interfaces

Cyclone III FPGAs support a broad range of external memory interfaces, such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM.

Device I/O Connectivity

With Cyclone III FPGAs, designers have the flexibility to implement a wide variety of I/O standards for their applications. Following table shows the overview of Cyclone III Device I/O connectivity.

Interface and Protocol Support

Cyclone III FPGAs support serial, bus, and network interfaces, as well as a wide range of communications protocols commonly used in industrial, communications, and consumer applications. Altera offers a variety of IP  cores for these protocols: 

• PCI Express
• PCI
• PCI-X
• SDRAM and SRAM Interfaces
• Ethernet Protocols
• Serial Bus Interfaces
• General consumer digital display standards
• General communications protocols

On-Chip Termination

Cyclone III devices include on-chip series termination (OCT), driver impedance matching for single-ended I/O standards. OCT helps to improve signal integrity, eliminate the need for external resistors and simplify PCB layout.
 

Application of the Cyclone III FPGAs

Cyclone III FPGAs in Wireless Applications

Cyclone III FPGAs deliver dedicated multipliers and lot of memory at a very low cost and very low power. These feature is suitable for wireless applications, including:

• Macro/Micro base station RF card/remote radio heads
• PicoCell or FemtoCell BTS
• WiMAX customer premise equipment (CPE)
• Software defined radio (SDR)

Following tables show some significant Cyclone III FPGA wireless application advantages:

Following figure shows an wireless application example, Cyclone III FPGA is used as a DSP coprocessor in WiMAX picocell base stations to implement scalable OFDMA engines and DDC and DUC functions. 

Cyclone III FPGA in WiMAX Application

Cyclone III FPGAs in Video and Image Processing Applications

Cyclone III FPGAs deliver abundant memory and dedicated multipliers. This features suitable for algorithmic-intensive applications such as video and image processing. Cyclone III FPGAs can be applied in a broad range of video applications, including video surveillance, broadcasting, image compression, and video conferencing.

One example here, with a Cyclone III FPGA, a low-cost H.264 encoder can be implemented. This solution supports over 16 channels in a single device.

H.264 Encoder using Cyclone III FPGA

Cyclone III FPGAs in Display Applications

The heart of the LCD HDTV is its image-processing and timing-control block. The image-processing block typically includes functions such as scan rate converter, frame rate converter, color decoder, motion detection, scalar, and deinterlacing.

LCD-TV Interface using Cyclone III FPGA

Development Tools for Cyclone III FPGAs

Altera offers the Cyclone III FPGA Development Kit. This economical development kit is an ideal introduction for beginner in  FPGA design. Several design tools and FPGA design examples is included in the kit.

Altera also offers free and commercial development tools. The free Quartus II Web Edition v7.0 can be retrieve freely from Altera.

Cyclone III FPGAs in Altera FAQ

Q: What is the Cyclone III FPGA family?

A: The 65-nm low-cost Cyclone III family is a low-power, high-functionality FPGA family supporting a wide range of cost-sensitive high-volume applications. Eight devices, ranging from 5K to 120K logic elements (LEs), offer up to 4 Mbits of memory, up to 288 embedded 18 x 18 multipliers, and a wide range of low-cost packages.

Q: What is unique about Cyclone III FPGAs?

A: Cyclone III FPGAs offer an unprecedented combination of low power consumption, high functionality, and low cost. Altera also offers the most complete and productive development tools with the free Quartus II Web Edition software version 7.0. Together, the productivity of the tools and the rich logic, digital signal processing (DSP), and memory resources of the Cyclone III family enable you to choose programmable logic over ASICs or ASSPs for more high-volume applications then ever before.

Q: How do Cyclone III devices compare with Cyclone II devices?

A: Compared to the previous generation built on the 90-nm process, the 65-nm Cyclone III family delivers:

1. 3.5X more embedded memory
2. 2X more embedded 18 x 18 multipliers
3. 20 percent lower cost per LE
4. 50 percent lower power consumption
5. Low-cost configuration options
6. Higher external memory interface speeds
7. More I/O and phase-locked loop (PLL) flexibility

Q: What is the power strategy behind the Cyclone III family?

A: Cyclone III FPGAs deliver lower power consumption due to TSMC’s 65-nm low-power (LP) process technology and the unique power management features in Quartus II software. TSMC’s LP process ensures low power consumption with a low leakage current, allowing operation in thermally challenging environments, eliminating or reducing cooling system costs, and extending battery life for portable applications. Further process advances include the use of low-k dielectrics and strained silicon.

Quartus II PowerPlay power analysis and optimization technology supports accurate analysis of dynamic and static power consumption, and push-button optimization of static and dynamic power consumption, while meeting speed and area requirements. Using these innovative techniques, Cyclone III FPGAs reduce power by up to 50 percent compared to the previous generation 90-nm Cyclone II FPGA family.

Q: What new applications do Cyclone III devices enable?

A: Cyclone III devices are ideal for high-volume applications in all market segments. Examples of what you can achieve exclusively with Cyclone III devices include:

• Broad range of new wireless applications, including bit rate, OFDMA symbol rate, and IF processing functions in wireless pico base stations
• Software-defined radio (SDR) waveform integration in a single device for less than 0.5 W of static power
• Video and image processing applications, such as integrating a four-channel H.264 standard-definition encoder in a single chip.
• Display applications, with the first low-cost FPGA support for all 1080p HDTV performance requirements

Source: Altera Cyclone III FPGAs