Altera announces 40-nm Stratix IV FPGAs and HardCopy IV ASICs

Altera has announced the new 40-nm Stratix IV FPGAs and
HardCopy IV ASICs. The Stratix IV family has up to 680K LEs (logic elements), 2X bigger
than Stratix III family. The HardCopy IV ASIC family features up to 13.3 million
gates and offers equivalent densities as the Stratix IV FPGAs. The new 40-nm
FPGAs satisfy high-end application in wide area of applications as ASIC prototyping.
broadcasting , wireless and wireline communications and also military
applications.

Altera Stratix IV FPGA

Key benefits of Stratix IV FPGAs:

• High density with up to 680K logic elements (LEs), 22.4 Mbits of embedded
  memory, and 1,360 18 x 18 multipliers
• High performance with a 2 speed grade advantage and the industry’s most
  advanced logic and routing architecture
• System bandwidth with up to 48 high-speed transceivers, at up to 8.5 Gbps
  and 1,067 Mbps (533 MHz) DDR3 memory interfaces
• Low power with up to 50 percent lower power than any other high-end FPGA
  in the market enabled by 40-nm benefits and Programmable Power Technology
• Hard intellectual property (IP) for PCI Express Gen1 (2.5 Gbps) and Gen2
  (5.0 Gbps) with up to four x8 blocks delivering a full endpoint or root-port
  function
• Superior signal integrity with the ability to drive a 50" backplane at
  6.375 Gbps with Plug & Play Signal Integrity

With the increasing demand for services such as video over Internet,
high-speed wireless data and digital TV, designers need to deliver solutions
that provide higher data rates, higher interface bandwidths, and increased data
processing all in a power-efficient manner. To address these design challenges,
Altera is leveraging its innovations in transceivers, memory interfaces,
low-power technology and FPGA core architecture to offer new capabilities with
its 40-nm devices.

The Stratix IV FPGA family is comprised
of two variants, an enhanced variant rich with memory and digital signal
processing (DSP) resources (Stratix IV E FPGAs) and an enhanced variant with
transceivers (Stratix IV GX FPGAs). Stratix IV GX FPGAs offer up to 48
transceivers operating at up to 8.5 Gbps, which provides designers with the
industry’s highest available bandwidth, more than twice the bandwidth of any
other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP)
support for PCI Express (PCIe) Gen 1 and 2 and also supports a wide range of
protocols including, Serial RapidIO, XAUI (including DDR XAUI), CPRI (including
6G CPRI), CEI 6G, Interlaken and Ethernet.

To address the low-power demands of customers, the Stratix IV family members
feature Altera’s patented Programmable Power Technology. This power-saving
technology optimizes logic, DSP and memory blocks to maximize performance where
needed while delivering the lowest power elsewhere in the design.

For the first time, Altera offers a transceiver-based ASIC option with the
new HardCopy IV ASIC family. Using the Stratix FPGAs in design delivers the
benefits of FPGA hardware and software co-design and co-verification—saving
months in time to market—and the use of HardCopy ASICs delivers the benefits of
ASICs in production.

Altera also enhance the company’s Quartus II design
software by delivering Quartus II
software v.8.0. This enhancement enables designers to achieve efficient team design and fast
development time through the high performance, logic utilization and fast compiling
time.

Engineering samples of the first member of the Stratix IV device family will
be available in Q4 2008. Customer tapeouts for
HardCopy IV ASICs will start in the Q3 2009.

More info about Stratix IV FPGAs and
HardCopy ASICs can be found at www.altera.com/stratix4 and www.altera.com/hardcopy4