45nm CMOS Design Platform SoC for Wireless and Portable Consumer Electronics - STMicroelectronics

STMicroelectronics unveiled details of its 45nm CMOS design platform for next-gen System-on-Chip (SoC), targeted for wireless and portable consumer electronics. The leading-edge 45nm low-power CMOS platform has already been used to complete, or tape-out, the design of a highly integrated 45nm demonstrator SoC device. This chip design includes an advanced dual-core CPU system and associated memory hierarchy, featuring the sophisticated low-power techniques required at the 45nm process technology node to combine new levels of performance with very low power consumption.

Laurent Bosson, STMicroelectronics, stated:

Early access to low-power 45nm CMOS technology is crucial to industry-leading manufacturers in their development of new wireless and portable consumer products, especially for next-generation 3G and 4G handheld multimedia terminals…

The silicon developed using ST's low-power 45nm CMOS platform will enable applications to combine very high performance with low power consumption…

The new low-power design platform, which takes full advantage of the multiple features and modularity of 45nm process technology, was developed at the STMicroelectronics site in Crolles, near Grenoble, France, and verified at the 300mm wafer facility operated by the Crolles2 Alliance.

In common with other 45nm platforms being readied for deployment, ST's low-power 45nm process features all of the advanced modules required for high density and high performance. These important modules include: 193nm immersion lithography for critical patterning layers; shallow-trench isolation and transistor stressors; advanced junction engineering, using millisecond anneal; and very low-k inter-metal copper dielectric, allowing reduced interconnect capacitances. In addition two cell libraries are available: one optimized for high performance and the other for low power consumption, giving designers a rich selection of options.

The 45nm design platform is fully supported by the industry-leading CAD tools from Cadence, Mentor Graphics, Synopsys and Magma through design solutions that have been developed in partnership between ST and the respective EDA companies' individual R&D groups, allowing customers to immediately begin designing advanced SoC solutions using familiar industry-standard tools.

Further technical details of the full 45nm library and design platform, include:

• Densities of up to 1600 Kgates per square mm are available, supporting a core supply of 1.1V, with metal pitches of 0.14-micron and from six to ten metal routing layers.
• Multiple library elements can be selected at the design level and used in the same design block, providing users of the platform with greater flexibility in optimizing performance and power consumption. This capability enables faster development of chips for use in high-performance and power-sensitive products.
• Power reduction techniques include adaptive vdd, low vdd operation, power shutdown, low standby current in retention mode, back bias and more.
• Extremely dense embedded memories: single-port memories using six-transistor SRAMcells, with area sizes down to 0.25 square micron.
• Full range of 1.8V I/O cells.
• A fully compatible low-cost process variant for embedded DRAM with threefold density improvement versus SRAM is under development.
• Additionally, the process has already recorded excellent results, including high-yield multi-Megabit SRAM test circuits, and fully functional SRAM test circuits operating at a supply voltage of 1.1V down to 0.9V.
• A broad portfolio of analog and radio-frequency IP (Intellectual Property) is under development to cover the need for a super-integrated single-chip system, while sophisticated digital IP modules such as microprocessors and DSPs will also be provided.

Source: STMicroelectronics 45nm CMOS Design Platform SoC